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148 条记录 (耗时 0.04 秒)

    Transistors including laterally extended active regions and methods of fabricating the same
    43.
    发明授权
    Transistors including laterally extended active regions and methods of fabricating the same 有权
    包括横向延伸的有源区的晶体管及其制造方法

    公开(公告)号：US07470588B2

    公开(公告)日：2008-12-30

    申请号：US11387029

    申请日：2006-03-22

    申请人： Min-Hee Cho ,  Ji-Young Kim

    发明人： Min-Hee Cho ,  Ji-Young Kim

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66621 ,  H01L21/823481 ,  H01L27/10876 ,  H01L29/78

    摘要： A transistor includes a substrate and an isolation region disposed in the substrate. The isolation regions defines an active region comprising upper and lower active regions, the upper active region having a first width and the lower active region having a second width greater than the first width. An insulated gate electrode extends through the upper active region and into the lower active region. Source and drain regions are disposed in the active region on respective first and second sides of the insulated gate electrode. The insulated gate electrode may include an upper gate electrode disposed in the upper active region and a lower gate electrode disposed in the lower active region, wherein the lower gate electrode is wider than the upper gate electrode. Related fabrication methods are described.

    摘要翻译： 晶体管包括衬底和设置在衬底中的隔离区。 隔离区域限定包括上部和下部有源区域的有源区域，上部有源区域具有第一宽度，而下部有源区域具有大于第一宽度的第二宽度。 绝缘栅电极延伸穿过上有源区并进入下有源区。 源极和漏极区域设置在绝缘栅电极的相应第一和第二侧上的有源区中。 绝缘栅电极可以包括设置在上有源区中的上栅电极和设置在下有源区中的下栅电极，其中下栅电极比上栅极电极宽。 描述相关的制造方法。

    Recess gate transistor structure for use in semiconductor device and method thereof
    45.
    发明授权
    Recess gate transistor structure for use in semiconductor device and method thereof 有权
    用于半导体器件的栅极晶体管结构及其方法

    公开(公告)号：US07378312B2

    公开(公告)日：2008-05-27

    申请号：US11608732

    申请日：2006-12-08

    申请人： Ji-Young Kim

    发明人： Ji-Young Kim

    IPC分类号： H01L21/8242 ,  H01L21/336 ,  H01L21/4763

    CPC分类号： H01L29/66621 ,  H01L29/7834

    摘要： An inner spacer is formed in a sidewall of a gate in contact with a first active region that is electrically connected to an upper capacitor, thereby reducing a gate induced drain leakage (GIDL). A structure of a recess gate transistor includes a gate insulation layer, a gate electrode, a first gate spacer, a second gate spacer and source/drain regions. The gate insulation layer is formed within a recess. The gate electrode is surrounded by the gate insulation layer and is extended from within the recess. The first gate spacer is spaced with a predetermined distance horizontally with a portion of the gate insulation layer, being formed in a sidewall of the gate electrode. The second gate spacer is formed in another part of the sidewall of the gate electrode. The source/drain regions are formed mutually oppositely on first and second active regions with the gate electrode therebetween.

    摘要翻译： 内部间隔件形成在栅极的侧壁中，与与上部电容器电连接的第一有源区域接触，由此减小栅极引起漏极泄漏（GIDL）。 凹槽栅极晶体管的结构包括栅极绝缘层，栅极电极，第一栅极间隔物，第二栅极间隔物和源极/漏极区域。 栅极绝缘层形成在凹部内。 栅电极被栅绝缘层包围，并从凹槽内延伸。 第一栅极间隔物与门极绝缘层的一部分水平地间隔预定距离，形成在栅电极的侧壁中。 第二栅极间隔物形成在栅电极的侧壁的另一部分中。 源极/漏极区域在第一和第二有源区域上彼此相对地形成，栅电极在它们之间。

    Semiconductor device and method of manufacturing the same
    46.
    发明授权
    Semiconductor device and method of manufacturing the same 失效
    半导体装置及其制造方法

    公开(公告)号：US07342275B2

    公开(公告)日：2008-03-11

    申请号：US11279080

    申请日：2006-04-07

    申请人： Byung-Jun Park ,  Ji-Young Kim

    发明人： Byung-Jun Park ,  Ji-Young Kim

    IPC分类号： H01L27/108

    CPC分类号： H01L21/76877 ,  H01L21/76831 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Wirings including first conductive layer patterns and insulating mask layer patterns are formed on a substrate. Insulating spacers are formed on sidewalls of the wirings. Self-aligned contact pads including portions of a second conductive layer are formed to contact with surfaces of the insulating spacers and to fill up a gap between the wirings. An interlayer dielectric layer is formed on the substrate where the contact pads are formed and is then partially etched to form contact holes exposing the contact pads. A selective epitaxial silicon layer is formed on the contact pads exposed through the contact holes to cover the insulating mask layer patterns. Thus, a short-circuit between the lower wiring and an upper wiring formed in the contact holes is prevented.

    摘要翻译： 在基板上形成包括第一导电层图案和绝缘掩模层图案的布线。 绝缘垫片形成在布线的侧壁上。 形成包括第二导电层的部分的自对准接触焊盘与绝缘间隔物的表面接触并填充布线之间的间隙。 在形成接触焊盘的基板上形成层间电介质层，然后将其部分地蚀刻以形成暴露接触焊盘的接触孔。 在通过接触孔暴露的接触焊盘上形成选择性外延硅层以覆盖绝缘掩模层图案。 因此，防止下布线和形成在接触孔中的上布线之间的短路。

    Semiconductor memory device and method for manufacturing the same
    47.
    发明授权
    Semiconductor memory device and method for manufacturing the same 有权
    半导体存储器件及其制造方法

    公开(公告)号：US07282405B2

    公开(公告)日：2007-10-16

    申请号：US11108929

    申请日：2005-04-18

    申请人： Ji-Young Kim

    发明人： Ji-Young Kim

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/10894 ,  H01L27/0207 ,  H01L27/10808 ,  H01L27/10885 ,  H01L27/10888

    摘要： A semiconductor memory device includes a plurality of bit line structures arranged in parallel on a semiconductor substrate and having a plurality of bit lines and an insulating material surrounding the bit lines, an isolation layer formed in a portion in spaces between the bit line structures to define a predetermined active region and having substantially the same height as the bit line structures, a semiconductor layer formed in the predetermined active region surrounded by the bit line structures and the isolation layer and having substantially the same height as the bit line structures and the isolation layer, a plurality of word line structures arranged in parallel on the bit line structures, the isolation layer, and the semiconductor layer, and comprising a plurality of word lines and an insulating material surrounding the word lines, and source and drain regions formed in the semiconductor layer on either side of the word line structures.

    摘要翻译： 半导体存储器件包括多个位线结构并行布置在半导体衬底上并且具有多个位线和围绕位线的绝缘材料，隔离层形成在位线结构之间的空间部分中以限定 预定的有源区并且具有与位线结构基本相同的高度;半导体层，形成在由位线结构和隔离层围绕的预定有源区中，并且具有与位线结构和隔离层基本相同的高度 ，在位线结构，隔离层和半导体层上平行布置的多个字线结构，并且包括多个字线和围绕字线的绝缘材料，以及形成在半导体中的源极和漏极区域 在字线结构的任一侧的层。

    Semiconductor device and method of manufacturing the same
    48.
    发明授权
    Semiconductor device and method of manufacturing the same 失效

    公开(公告)号：US07259069B2

    公开(公告)日：2007-08-21

    申请号：US11229202

    申请日：2005-09-15

    申请人： Nak-Jin Son ,  Ji-Young Kim

    发明人： Nak-Jin Son ,  Ji-Young Kim

    IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L21/331

    CPC分类号： H01L29/66651 ,  H01L27/10873 ,  H01L29/1041 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/78

    摘要： A semiconductor device and a method of manufacturing the same is disclosed. A trench is formed in an active region of a semiconductor substrate. A doped layer is formed on the inner walls of the trench. The trench is filled up with a first semiconductor layer. A gate insulating layer is formed on the first semiconductor layer and the substrate. Two gate electrodes are formed on the gate insulating layer such that the trench is located in between two gate electrodes. First and second impurity regions are formed in the substrate on both sides of each of the gate electrodes. Since the doped layer is locally formed in the trench area, the source and drain regions are completely separated from the heavily doped layer to weaken the electric field of PN junction, thereby improving refresh and preventing punchthrough between the source and drain.

    Method of forming dual gate dielectric layer
    49.
    发明授权
    Method of forming dual gate dielectric layer 有权
    形成双栅介电层的方法

    公开(公告)号：US07169681B2

    公开(公告)日：2007-01-30

    申请号：US10964170

    申请日：2004-10-12

    申请人： Min-Hee Cho ,  Ji-Young Kim

    发明人： Min-Hee Cho ,  Ji-Young Kim

    IPC分类号： H01L21/76

    CPC分类号： H01L21/823481 ,  H01L21/76229 ,  H01L21/823462

    摘要： A method of forming a dual gate dielectric layer increases a performance of a semiconductor device by using a dielectric layer having a high dielectric constant, including forming a first dielectric layer having a predetermined thickness on a semiconductor substrate; removing the first dielectric layer formed on a second region, but leaving this layer on a first region; and forming a second dielectric layer having a dielectric constant higher than that of the first dielectric layer, on the first and second regions.

    摘要翻译： 通过使用具有高介电常数的介电层，包括在半导体衬底上形成具有预定厚度的第一介质层，形成双栅介质层的方法提高了半导体器件的性能; 去除形成在第二区域上的第一介电层，但将该层留在第一区域上; 以及在所述第一和第二区域上形成具有高于所述第一介电层的介电常数的介电常数的第二电介质层。

    Recessed gate transistor structure and method of forming the same
    50.
    发明授权
    Recessed gate transistor structure and method of forming the same 有权
    嵌入式晶体管结构及其形成方法

    公开(公告)号：US07153745B2

    公开(公告)日：2006-12-26

    申请号：US10963928

    申请日：2004-10-12

    申请人： Min-Hee Cho ,  Ji-Young Kim

    发明人： Min-Hee Cho ,  Ji-Young Kim

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66621 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/7834

    摘要： Recessed gate transistor structures and methods for making the same prevent a short between a gate conductive layer formed on a non-active region and an active region by forming an insulation layer therebetween, even though a misalignment is generated in forming a gate. The method and structure reduce the capacitance between gates. The method includes forming a device isolation film for defining an active region and a non-active region, on a predetermined region of a semiconductor substrate. First and second insulation layers are formed on an entire face of the substrate. A recess is formed in a portion of the active region. A gate insulation layer is formed within the recess, and then a first gate conductive layer is formed within the recess. A second gate conductive layer is formed on the second insulation layer and the first gate conductive layer. Subsequently, source/drain regions are formed.

    摘要翻译： 嵌入栅极晶体管结构及其制造方法即使在形成栅极时产生不对准，也可以通过在其间形成绝缘层来防止形成在非有源区上的栅极导电层与有源区之间的短路。 该方法和结构降低了门之间的电容。 该方法包括在半导体衬底的预定区域上形成用于限定有源区和非有源区的器件隔离膜。 第一和第二绝缘层形成在基板的整个表面上。 在有源区域的一部分中形成凹部。 在凹部内形成栅极绝缘层，然后在凹部内形成第一栅极导电层。 第二栅极导电层形成在第二绝缘层和第一栅极导电层上。 随后，形成源/漏区。