公开(公告)号：US5529946A

公开(公告)日：1996-06-25

申请号：US497270

申请日：1995-06-30

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/70

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/91 ,  Y10S148/014

摘要： A process of fabricating the storage capacitor for a dynamic random access memory cell which includes a transistor with gate electrode and source/drain regions on a surface of a substrate. The process forms a polysilicon layer which is coupled to one of the source/drain regions, over the transistor structure. A mask is formed to cover the planned capacitor area, and then the non-masked portion of the polysilicon layer is removed. Liquid phase deposition oxide is formed on the area not masked by the mask, and then the mask is stripped. A polysilicon sidewall spacer is formed on the sidewalls of the LPD oxide, and connects with the remaining polysilicon layer to jointly form a first capacitor electrode. The LPD oxide is removed, followed by forming a dielectric layer along the surface of the first capacitor electrode. A second capacitor electrode made from polysilicon is formed along the surface of the dielectric layer to complete the storage capacitor structure.

摘要翻译： 制造用于动态随机存取存储单元的存储电容器的过程包括在基板的表面上具有栅电极和源/漏区的晶体管。 该工艺形成多晶硅层，该多晶硅层在晶体管结构上耦合到源/漏区中的一个。 形成掩模以覆盖预定的电容器区域，然后去除多晶硅层的未屏蔽部分。 在未被掩模掩蔽的区域上形成液相沉积氧化物，然后剥离掩模。 在LPD氧化物的侧壁上形成多晶硅侧壁间隔物，并与剩余的多晶硅层连接，共同形成第一电容器电极。 除去LPD氧化物，然后沿着第一电容器电极的表面形成电介质层。 沿着电介质层的表面形成由多晶硅制成的第二电容器电极，以完成存储电容器结构。

公开(公告)号：US5489543A

公开(公告)日：1996-02-06

申请号：US347880

申请日：1994-12-01

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L21/8234

CPC分类号： H01L29/66583 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/7833

摘要： A method of forming a MOS device having a localized anti-punchthrough region, which is adjacent to but is not in contact with source/drain regions of the MOS device. A trench is formed by depositing a conducting layer on an oxide layer located on a channel region of the MOS device. The trench is used as a self-alignment mask for a subsequent implantation process to form the localized anti-punchthrough region.

摘要翻译： 一种形成具有与MOS器件的源极/漏极区域相邻但不接触的局部抗穿通区域的MOS器件的方法。 通过在位于MOS器件的沟道区上的氧化物层上沉积导电层来形成沟槽。 沟槽用作自对准掩模，用于随后的注入工艺以形成局部的抗穿透区域。

公开(公告)号：US5484744A

公开(公告)日：1996-01-16

申请号：US422291

申请日：1995-04-14

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L21/8242 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10852

摘要： The present invention provides a method of fabricating a DRAM cell capacitor having an improved capacitance by increasing the surface area of the electrode plate. First, a first insulating layer, a second insulating layer, and a barrier layer are formed sequentially on a semiconductor substrate having source/drain regions. Next, a portion of the barrier layer is etched to form a first contact opening over one of the source/drain regions. A first sidewall spacer is formed on the sidewall of the first contact opening of the barrier layer. Similarly, a second contact opening is formed by etching the second insulating layer using the barrier layer and the first sidewall spacer as a mask, and a second sidewall spacer is formed on the sidewall of the second contact opening of the second insulating layer. Then, a third contact opening is formed by etching the first insulating layer using the first sidewall spacer, the second sidewall spacer, and the second insulating layer as a mask, meanwhile the barrier layer is also removed. After removing the second sidewall spacer, a first electrode plate is formed overlying the exposed surfaces of the first sidewall spacer, the second insulating layer, the first insulating layer, and the semiconductor substrate. Hence, the first electrode plate is connected to one of the source/drain regions through the third contact opening. Finally, a dielectric layer is formed on the first electrode plate, and a second electrode plate is formed on the dielectric layer to complete the capacitor fabrication.

摘要翻译： 本发明提供通过增加电极板的表面积来制造具有改善的电容的DRAM单元电容器的方法。 首先，在具有源极/漏极区域的半导体衬底上依次形成第一绝缘层，第二绝缘层和势垒层。 接下来，蚀刻阻挡层的一部分以在源极/漏极区域之一上形成第一接触开口。 第一侧壁间隔件形成在阻挡层的第一接触开口的侧壁上。 类似地，通过使用阻挡层和第一侧壁间隔物作为掩模蚀刻第二绝缘层来形成第二接触开口，并且在第二绝缘层的第二接触开口的侧壁上形成第二侧壁间隔物。 然后，通过使用第一侧壁间隔件，第二侧壁间隔件和第二绝缘层作为掩模蚀刻第一绝缘层来形成第三接触开口，同时还去除阻挡层。 在去除第二侧壁间隔物之后，形成第一电极板，覆盖第一侧墙，第二绝缘层，第一绝缘层和半导体衬底的暴露表面。 因此，第一电极板通过第三接触开口连接到源/漏区中的一个。 最后，在第一电极板上形成电介质层，在电介质层上形成第二电极板以完成电容器制造。

公开(公告)号：US5473179A

公开(公告)日：1995-12-05

申请号：US304693

申请日：1994-09-12

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L21/28 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/51 ,  H01L29/788 ,  H01L29/78

CPC分类号： H01L27/11517 ,  H01L27/115 ,  H01L29/511 ,  H01L29/7883 ,  H01L21/28211 ,  Y10S148/114

摘要： A new method of obtaining a consistent controllable tunnel oxide near the source/drain edge of a contactless memory cell is described. A thick gate oxide layer is grown on a semiconductor substrate. A first polysilicon layer is deposited overlying the thick gate oxide layer. A silicon nitride layer followed by a silicon oxide layer are deposited overlying the first polysilicon layer. The silicon oxide, silicon nitride, and first polysilicon layers are patterned and etched. Arsenic ions are implanted through the thick gate oxide layer into the substrate to form buried source and drain bit lines within the substrate. A second layer of silicon nitride is deposited over the patterned layers and anisotropically etched to form sidewall spacers. SATO (self-aligned thick oxide) oxidation is performed over the N+ area. The silicon nitride spacers are etched away whereby a portion of the thick gate oxide underlying the spacers is exposed. The silicon oxide layer is removed along with the exposed thick gate oxide. The thin tunnel oxide is regrown in the region where the silicon nitride spacers were removed. The silicon nitride layer is removed followed by deposition of a second layer of polysilicon overlying the first polysilicon layer. This layer is patterned such that it is overlying the SATO area to form the floating gate. An interpoly dielectric layer is deposited followed by a third polysilicon layer which is deposited and patterned to form the control gate completing formation of the memory cell.

摘要翻译： 描述了在非接触式存储器单元的源极/漏极边缘附近获得一致的可控隧道氧化物的新方法。 在半导体衬底上生长厚栅氧化层。 沉积在厚栅极氧化物层上的第一多晶硅层。 在第一多晶硅层上沉积氮化硅层，随后是氧化硅层。 氧化硅，氮化硅和第一多晶硅层被图案化和蚀刻。 将砷离子通过厚栅极氧化物层注入到衬底中，以在衬底内形成掩埋源极和漏极位线。 第二层氮化硅沉积在图案化层上并各向异性蚀刻以形成侧壁间隔物。 在N +区域上进行SATO（自对准厚氧化物）氧化。 蚀刻氮化硅间隔物，由此暴露间隔物下方的厚栅极氧化物的一部分。 氧化硅层与暴露的厚栅氧化物一起被去除。 在去除氮化硅间隔物的区域中再生长薄的氧化隧道。 去除氮化硅层，然后沉积覆盖在第一多晶硅层上的第二多晶硅层。 该层被图案化，使得它覆盖在SATO区域上以形成浮动栅极。 沉积多层介电层，随后沉积和图案化第三多晶硅层，以形成完成存储单元形成的控制栅极。

公开(公告)号：US5472898A

公开(公告)日：1995-12-05

申请号：US287949

申请日：1994-08-09

申请人： Gary Hong ,  Chen-Chiu Hsue

发明人： Gary Hong ,  Chen-Chiu Hsue

IPC分类号： H01L21/8246 ,  H01L21/265

CPC分类号： H01L27/1126

摘要： A self-aligned coding process for mask ROM is disclosed. First, a substrate having a plurality of bit-lines formed therein, a gate oxide layer formed on the bit-lines, and a plurality of word-lines formed on the gate oxide, which together construct an array of memory cells, is provided. Next, a barrier layer is formed on the word-lines. A silicon dioxide layer is formed on the gate oxide between the word-lines by using liquid phase deposition, wherein the thickness of the silicon dioxide layer is larger than that of the word-lines. Then, the barrier layer is removed. A mask layer is formed on the substrate exposing parts of the memory cells that will be programmed. Finally, impurities are implanted into the substrate not covered by the mask layer and the silicon dioxide layer to make the memory cells that will be programmed operating in a first state, and leave other non-programmed memory cells operating in a second state.

摘要翻译： 公开了一种用于掩模ROM的自对准编码处理。 首先，提供一种形成在其中的多个位线的衬底，形成在位线上的栅极氧化层，以及形成在栅极氧化物上的多个字线，这些字线一起构成存储单元阵列。 接下来，在字线上形成阻挡层。 通过使用液相沉积在字线之间的栅极氧化物上形成二氧化硅层，其中二氧化硅层的厚度大于字线的厚度。 然后，去除阻挡层。 在衬底上形成露出将被编程的存储器单元的部分的掩模层。 最后，将杂质注入到未被掩模层和二氧化硅层覆盖的衬底中，以使将被编程的存储器单元在第一状态下工作，并使其它非编程存储器单元在第二状态下工作。

公开(公告)号：US5449638A

公开(公告)日：1995-09-12

申请号：US254532

申请日：1994-06-06

申请人： Gary Hong ,  Chen-Chiu Hsue ,  H. J. Wu ,  Lawrence Y. Lin

发明人： Gary Hong ,  Chen-Chiu Hsue ,  H. J. Wu ,  Lawrence Y. Lin

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76251 ,  Y10S148/012 ,  Y10S148/135

摘要： A method for forming a thin, uniform top silicon layer using bonded-wafer SOI technology is described. A dielectric layer is formed on a first surface of a first silicon substrate. A trench is formed in a first surface of a second silicon substrate. A polishing stopper is formed in the trench. A second dielectric layer with a smooth top surface is formed over the polishing stopper and over the first surface of the second silicon substrate. The smooth top surface of the second dielectric layer of the second silicon substrate is bonded to the dielectric layer of the first silicon substrate. Material is removed from the exposed surface of the second silicon substrate to form the silicon layer with well-controlled thickness, having a top surface co-planar with the polishing stopper.

摘要翻译： 描述了使用接合晶片SOI技术形成薄的均匀顶部硅层的方法。 介电层形成在第一硅衬底的第一表面上。 在第二硅衬底的第一表面中形成沟槽。 在沟槽中形成抛光止动件。 在抛光止动器上方并在第二硅衬底的第一表面上形成具有平滑顶表面的第二电介质层。 第二硅衬底的第二电介质层的平滑顶表面结合到第一硅衬底的电介质层。 从第二硅衬底的暴露表面去除材料以形成具有良好控制厚度的硅层，其具有与抛光止挡件共面的顶表面。

公开(公告)号：US5432106A

公开(公告)日：1995-07-11

申请号：US100305

申请日：1993-08-02

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L21/336 ,  H01L29/788 ,  H01L21/22

CPC分类号： H01L29/66825 ,  H01L29/7885

摘要： An EPROM memory cell and its fabrication are described. The semiconductor substrate is a first conductivity type. The process begins by forming a conductive gate overlying the substrate, but electrically insulated therefrom by a layer of a first dielectric material. The gate includes a first conductive material, a second layer of dielectric material, and a second conductive layer. A sidewall dielectric spacer is formed adjacent to an edge of the gate. Ions are implanted into the substrate of a species of an opposite conductivity type, at a substantial acute angle relative to a vertical angle with respect to the substrate, with the spacer protecting the substrate from ion implantation adjacent to the gate. Alternatively, the sidewall can be formed subsequent to the second deposition of doping ions at an acute angle.

摘要翻译： 描述了EPROM存储单元及其制造。 半导体衬底是第一导电类型。 该过程开始于形成覆盖衬底的导电栅极，但是通过第一电介质材料层与其电绝缘。 栅极包括第一导电材料，第二介电材料层和第二导电层。 在栅极的边缘附近形成侧壁电介质间隔物。 离子以相对于衬底相对于垂直角度的相当锐角的相反导电类型的衬底的衬底中注入，衬垫保护衬底免受邻近栅极的离子注入。 或者，可以在以锐角第二次沉积掺杂离子之后形成侧壁。

公开(公告)号：US5429970A

公开(公告)日：1995-07-04

申请号：US276605

申请日：1994-07-18

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L21/8247 ,  H01L21/266

CPC分类号： H01L27/11521

摘要： A new method of obtaining an improved coupling ratio and short channel effect in a Flash EEPROM memory cell is shown. A trench is etched into a semiconductor substrate. A thick gate oxide layer is formed over the surface of the substrate and within the trench. A layer of silicon nitride is deposited and anisotropically etched away to leave spacers on the sidewalls of the trench. The spacers are overetched to expose an upper portion of the gate oxide layer on the trench sidewalls. The gate oxide layer not covered by the spacers is removed, exposing the horizontal silicon surface of the substrate in the bottom of the trench and the upper portion of the silicon sidewalls of the trench above the spacers. A tunnel oxide layer is grown on the exposed silicon surfaces of the substrate and within the trench wherein the controllable small area of tunnel oxide within the trench provides an improved coupling ratio and the long channel afforded by the trenched channel region improves the short channel effect of the memory cell. The silicon nitride spacers are removed. A first polysilicon layer is deposited within the trench. An interpoly dielectric layer is deposited over the first polysilicon layer followed by a second polysilicon layer. The layers are patterned to form a stacked polysilicon structure wherein the first polysilicon layer forms a floating gate and the second polysilicon layer forms a control gate. Source and drain regions are formed on either side of the stacked polysilicon structure.

摘要翻译： 示出了在闪速EEPROM存储器单元中获得改进的耦合比和短沟道效应的新方法。 将沟槽蚀刻到半导体衬底中。 在衬底的表面上和沟槽内形成厚栅氧化层。 沉积氮化硅层并各向异性地蚀刻掉，以在沟槽的侧壁上留下间隔物。 将间隔物过蚀刻以暴露沟槽侧壁上的栅氧化层的上部。 没有被间隔物覆盖的栅极氧化物层被去除，暴露沟槽底部的衬底的水平硅表面和间隔物上方的沟槽的硅侧壁的上部。 隧道氧化物层生长在衬底的暴露的硅表面上并且在沟槽内，其中沟槽内的隧道氧化物的可控小区域提供改进的耦合比，并且由沟槽沟道区域提供的长沟道改善了短沟道效应 存储单元。 去除氮化硅间隔物。 第一多晶硅层沉积在沟槽内。 在第一多晶硅层上沉积多层介电层，随后沉积第二多晶硅层。 图案化层以形成堆叠多晶硅结构，其中第一多晶硅层形成浮置栅极，第二多晶硅层形成控制栅极。 源极和漏极区域形成在堆叠多晶硅结构的两侧。

公开(公告)号：US5427970A

公开(公告)日：1995-06-27

申请号：US276604

申请日：1994-07-18

申请人： Chen-Chih Hsue ,  Gary Hong

发明人： Chen-Chih Hsue ,  Gary Hong

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/265

CPC分类号： H01L29/66825 ,  H01L21/28141

摘要： A new method of fabricating a high coupling ratio Flash EEPROM memory cell is achieved. A layer of silicon dioxide is provided over the surface of a semiconductor substrate. A layer of silicon nitride is deposited over the silicon dioxide layer and patterned. The silicon dioxide layer not covered by the patterned silicon nitride layer is removed, thereby exposing portions of the substrate. A tunnel oxide layer is grown on the exposed portions of the semiconductor substrate. Silicon nitride spacers are formed on the sidewalls of the patterned silicon nitride layer. Ions are implanted into the substrate using the silicon nitride layer and spacers as a mask to form implanted regions within the semiconductor substrate. The semiconductor substrate is oxidized where the implanted regions have been formed leaving the thin tunnel oxide only under the silicon nitride spacers. The silicon nitride layer and spacers are removed. A first polysilicon layer is deposited over the surface of the silicon dioxide and tunnel oxide layers and patterned to form a floating gate. An interpoly dielectric layer is deposited over the patterned first polysilicon layer followed by a second polysilicon layer. The second polysilicon layer is patterned to form a control gate. Passivation and metallization complete the fabrication of the memory cell with improved coupling ratio.

摘要翻译： 实现了一种制造高耦合比闪存EEPROM存储单元的新方法。 在半导体衬底的表面上设置一层二氧化硅。 一层氮化硅沉积在二氧化硅层上并构图。 未被图案化氮化硅层覆盖的二氧化硅层被去除，从而暴露衬底的部分。 在半导体衬底的暴露部分上生长隧道氧化物层。 在图案化氮化硅层的侧壁上形成氮化硅间隔物。 使用氮化硅层和间隔物作为掩模将离子注入到衬底中，以在半导体衬底内形成注入区域。 半导体衬底被氧化，其中已经形成注入区域，仅在氮化硅间隔物之下留下薄的隧道氧化物。 去除氮化硅层和间隔物。 第一多晶硅层沉积在二氧化硅和隧道氧化物层的表面上并被图案化以形成浮栅。 在图案化的第一多晶硅层之后沉积多层介电层，随后是第二多晶硅层。 图案化第二多晶硅层以形成控制栅极。 钝化和金属化完成了具有改进的耦合比的存储器单元的制造。

公开(公告)号：US5382545A

公开(公告)日：1995-01-17

申请号：US158385

申请日：1993-11-29

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L21/44 ,  H01L21/48

CPC分类号： H01L21/76801 ,  H01L21/76897 ,  H01L23/5226 ,  H01L2924/0002

摘要： A device and a method of formation on a substrate of a semiconductor interconnection via structure for semiconductor devices is provided. Initially, form a first metal layer on the substrate, a first dielectric layer upon the first metal layer, and a mask upon the dielectric layer with a metal etching pattern therein. Then, etch through the first dielectric layer and the first metal layer to the substrate forming trenches between metal lines formed from the first metal layer covered with the dielectric layer. Next, form a first etch stop layer upon the surface of the first dielectric layer and planarize it, a second dielectric layer above the etch stop layer, and a second etch stop layer on the second dielectric layer. Then, pattern the second dielectric and the second etch stop layer and etch to form a via hole down to a surface of the first metal layer. Then, form a second metal layer and a metal plug in the via hole extending into contact with the first metal layer.

摘要翻译： 提供了一种用于半导体器件的半导体互连通孔结构的衬底上的器件和方法。 首先，在基板上形成第一金属层，在第一金属层上形成第一介电层，在介质层上形成具有金属蚀刻图案的掩模。 然后，通过第一介电层和第一金属层蚀刻到由覆盖有电介质层的第一金属层形成的金属线之间形成沟槽的衬底。 接下来，在第一介电层的表面上形成第一蚀刻停止层并使其平坦化，在蚀刻停止层上方的第二介电层和第二介电层上的第二蚀刻停止层。 然后，对第二电介质和第二蚀刻停止层进行图案化并蚀刻以形成到第一金属层的表面的通孔。 然后，在通孔中形成与第一金属层接触的第二金属层和金属塞。