公开(公告)号：US06352917B1

公开(公告)日：2002-03-05

申请号：US09598691

申请日：2000-06-21

申请人： Subhash Gupta ,  Mei-Sheng Zhou ,  Simon Chooi ,  Sangki Hong

发明人： Subhash Gupta ,  Mei-Sheng Zhou ,  Simon Chooi ,  Sangki Hong

IPC分类号： H01L214763

CPC分类号： H01L21/76885 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A new method of forming metal interconnect levels containing damascene interconnects and via plugs in the manufacture of an integrated circuit device has been achieved. The method creates a reversed dual damascene structure. A first dielectric layer is provided overlying a semiconductor substrate. The dielectric layer is patterned to form trenches for planned damascene interconnects. Insulating spacers may optionally be formed on the trench sidewalls. A conductive barrier layer is deposited overlying the dielectric layer and lining the trenches. A metal layer, preferably comprising copper, is deposited overlying the conductive barrier layer and filling the trenches. The metal layer and the conductive barrier layer are polished down to thereby form the damascene interconnects. A passivation layer may optionally be deposited. The damascene interconnects are patterned to form via plugs overlying the damascene interconnects. The patterning comprises partially etching down the damascene interconnects using a via mask overlying and protecting portions of the damascene interconnects. A trench mask also overlies and protects the first dielectric layer from metal contamination during the etching down.

摘要翻译： 已经实现了在集成电路器件的制造中形成包含镶嵌互连和通孔插塞的金属互连级别的新方法。 该方法创建一个反向的双镶嵌结构。 第一电介质层设置在半导体衬底上。 图案化电介质层以形成用于计划的大马士革互连的沟槽。 可以可选地在沟槽侧壁上形成绝缘间隔物。 导电阻挡层沉积在电介质层上并衬在沟槽上。 沉积优选包含铜的金属层，覆盖在导电阻挡层上并填充沟槽。 金属层和导电阻挡层被抛光，从而形成镶嵌互连。 可以任选地沉积钝化层。 大马士革互连被图案化以形成覆盖大马士革互连的通孔塞。 图案化包括使用覆盖并保护大马士革互连部分的通孔掩模部分地蚀刻镶嵌互连。 在蚀刻过程中，沟槽掩模也覆盖并保护第一介电层免受金属污染。

公开(公告)号：US06225202B1

公开(公告)日：2001-05-01

申请号：US09598689

申请日：2000-06-21

申请人： Subhash Gupta ,  Mei-Sheng Zhou ,  Simon Chooi ,  Sangki Hong

发明人： Subhash Gupta ,  Mei-Sheng Zhou ,  Simon Chooi ,  Sangki Hong

IPC分类号： H01L214763

CPC分类号： H01L29/665 ,  C23F4/00 ,  H01L21/32136

摘要： A method for removing unreacted nickel or cobalt after silicidation using carbon monoxide dry stripping is described. Shallow trench isolation regions are formed in a semiconductor substrate surrounding and electrically isolating an active area from other active areas. A gate electrode and associated source and drain regions are formed in the active area wherein dielectric spacers are formed on sidewalls of the gate electrode. A nickel or cobalt layer is deposited over the gate electrode and associated source and drain regions, shallow trench isolation regions, and dielectric spacers. The semiconductor substrate is annealed whereby the nickel or cobalt layer overlying the gate electrode and said source and drain regions is transformed into a nickel or cobalt silicide layer and wherein the nickel or cobalt layer overlying the dielectric spacers and the shallow trench isolation regions is unreacted. The unreacted nickel or cobalt layer is exposed to a plasma containing carbon monoxide gas wherein the carbon monoxide gas reacts with the unreacted nickel or cobalt thereby removing the unreacted nickel or cobalt from the substrate to complete salicidation of the integrated circuit device.

摘要翻译： 描述了使用一氧化碳干燥汽提在硅化后除去未反应的镍或钴的方法。 在半导体衬底中形成浅沟槽隔离区域，该半导体衬底围绕并使活性区域与其它有源区域电隔离。 在有源区域中形成栅电极和相关源极和漏极区，其中在栅电极的侧壁上形成有电介质间隔物。 在栅极电极和相关的源极和漏极区域，浅沟槽隔离区域和介电间隔物上沉积镍或钴层。 半导体衬底被退火，由此将覆盖在栅电极和所述源极和漏极区域上的镍或钴层转变成镍或钴硅化物层，并且其中覆盖电介质间隔物和浅沟槽隔离区的镍或钴层是未反应的。 将未反应的镍或钴层暴露于含有一氧化碳气体的等离子体中，其中一氧化碳气体与未反应的镍或钴反应，从而从基板除去未反应的镍或钴，以完成集成电路器件的水化。

公开(公告)号：US6114243A

公开(公告)日：2000-09-05

申请号：US439361

申请日：1999-11-15

申请人： Subhash Gupta ,  Kwok Keung Paul Ho ,  Mei-Sheng Zhou ,  Simon Chool

发明人： Subhash Gupta ,  Kwok Keung Paul Ho ,  Mei-Sheng Zhou ,  Simon Chool

IPC分类号： H01L21/302 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/76865 ,  H01L21/76877

摘要： A new method to prevent copper contamination of the intermetal dielectric layer during via or dual damascene etching by forming a capping layer over the first copper metallization is described. A first copper metallization is formed in a dielectric layer overlying a semiconductor substrate wherein a barrier metal layer is formed underlying the first copper metallization and overlying the dielectric layer. The first copper metallization is planarized, then etched to form a recess below the surface of the dielectric layer. A conductive capping layer is deposited overlying the first copper metallization within the recess and overlying the dielectric layer. The conductive capping layer is removed except over the first copper metallization within the recess using one of several methods. An intermetal dielectric layer is deposited overlying the dielectric layer and the conductive capping layer overlying the first copper metallization. A via or dual damascene opening is etched through the intermetal dielectric layer to the conductive capping layer wherein the conductive capping layer prevents copper contamination of the intermetal dielectric layer during etching. The via or dual damascene opening is filled with a metal layer to complete electrical connections in the fabrication of an integrated circuit device.

摘要翻译： 描述了在通过或双镶嵌蚀刻期间通过在第一铜金属化上形成覆盖层来防止金属间电介质层的铜污染的新方法。 第一铜金属化形成在覆盖半导体衬底的电介质层中，其中阻挡金属层形成在第一铜金属化层下方并且覆盖在电介质层上。 第一铜金属化被平坦化，然后被蚀刻以在介电层的表面下方形成凹陷。 导电覆盖层沉积在凹槽内的第一铜金属化层上并覆盖在介电层上。 使用几种方法之一除去在凹槽内的第一铜金属化之外除去导电覆盖层。 覆盖介电层和覆盖第一铜金属化的导电覆盖层的金属间电介质层被沉积。 通孔或双镶嵌开口通过金属间电介质层被蚀刻到导电覆盖层，其中导电覆盖层防止蚀刻期间金属间介电层的铜污染。 通孔或双镶嵌开口填充有金属层，以在集成电路器件的制造中完成电连接。

公开(公告)号：US06255266B1

公开(公告)日：2001-07-03

申请号：US09659728

申请日：2000-09-11

申请人： Subhash Gupta ,  Simon Choo I ,  Mei Sheng Zhou ,  Paul Ho

发明人： Subhash Gupta ,  Simon Choo I ,  Mei Sheng Zhou ,  Paul Ho

IPC分类号： C11D904

CPC分类号： C11D3/2072 ,  C11D3/2003 ,  C11D3/2093 ,  C11D3/3945 ,  C23G5/032 ,  Y10S134/902

摘要： A method of cleaning elemental copper, cobalt, or nickel from the surface of equipment hardware without corroding or damaging the equipment parts and surfaces in the event of wafer breakage and non-wafer breakage is described. A solution comprising an alkyldione peroxide, a stabilizing agent, and alcohols is used to oxidize the metal and form soluble complexes which are removed by the cleaning solution. Also, a novel alkyldione peroxide solution for cleaning elemental copper, cobalt, or nickel from the surface of equipment hardware in the event of wafer breakage and non-wafer breakage is provided.

摘要翻译： 描述了从设备硬件表面清除元素铜，钴或镍的方法，而不会在晶片断裂和非晶片断裂的情况下腐蚀或损坏设备部件和表面。 使用包含烷基二酮过氧化物，稳定剂和醇的溶液来氧化金属并形成被清洁溶液除去的可溶性络合物。 此外，提供了在晶片断裂和非晶片断裂的情况下从设备硬件的表面清除元素铜，钴或镍的新型烷基二氧化物溶液。

公开(公告)号：US06465157B1

公开(公告)日：2002-10-15

申请号：US09494638

申请日：2000-01-31

申请人： Jianxun Li ,  Mei Sheng Zhou ,  Subhash Gupta ,  Ming hui Far

发明人： Jianxun Li ,  Mei Sheng Zhou ,  Subhash Gupta ,  Ming hui Far

IPC分类号： G03F700

CPC分类号： H01L21/76811

摘要： A new method of forming dual damascene interconnects has been achieved. A semiconductor substrate is provided. A dielectric layer is provided overlying the semiconductor substrate. A first photoresist layer is deposited overlying the dielectric layer. The first photoresist layer is exposed, but not developed, to define patterns where via trenches are planned. A second photoresist layer is deposited overlying the first photoresist layer. The second photoresist layer is exposed to define patterns where interconnect trenches are planned. The second photoresist layer and the first photoresist layer are developed to complete the via trench pattern of the first photoresist layer and the interconnect trench pattern of the second photoresist layer. The dielectric layer is etched through where defined by the via trench pattern of the first photoresist layer. The dielectric layer is etch where defined by the interconnect pattern of the second photoresist layer, and the dual damascene interconnect of the integrated circuit device is completed.

摘要翻译： 已经实现了形成双镶嵌互连的新方法。 提供半导体衬底。 提供覆盖在半导体衬底上的电介质层。 沉积在介电层上的第一光致抗蚀剂层。 第一光致抗蚀剂层被暴露但未显影，以限定通过沟槽被规划的图案。 第二光致抗蚀剂层沉积在第一光致抗蚀剂层上。 暴露第二光致抗蚀剂层以限定互连沟槽被计划的图案。 显影第二光致抗蚀剂层和第一光致抗蚀剂层以完成第一光致抗蚀剂层的通孔沟槽图案和第二光致抗蚀剂层的互连沟槽图案。 电介质层被蚀刻到由第一光致抗蚀剂层的通孔沟槽图案限定的位置。 介电层是由第二光致抗蚀剂层的互连图案限定的蚀刻，并且完成集成电路器件的双镶嵌互连。

公开(公告)号：US06740580B1

公开(公告)日：2004-05-25

申请号：US09389633

申请日：1999-09-03

申请人： Subhash Gupta ,  Chyi S. Chern ,  Mei Sheng Zhou

发明人： Subhash Gupta ,  Chyi S. Chern ,  Mei Sheng Zhou

IPC分类号： H01L214763

CPC分类号： H01L21/76846 ,  H01L21/76873 ,  H01L21/76874 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method to form copper interconnects is described. The method may be used to form single or dual damascene interconnects. The addition of an aluminum barrier layer to the conventional barrier layer creates a superior barrier to copper diffusion. A substrate layer is provided. A dielectric layer is deposited overlying the substrate layer. The dielectric layer patterned to form interconnect trenches. An optional titanium adhesion layer may be deposited. An aluminum barrier layer is deposited overlying the interior surfaces of the trenches. A second barrier layer, comprising for instance titanium and titanium nitride, is deposited overlying the aluminum barrier layer. A copper layer is deposited overlying the second barrier layer and filling the interconnect trenches. The copper layer, the second barrier layer, and the aluminum barrier layer are polished down to the top surface of the dielectric layer to define the copper interconnects, and complete the fabrication of the integrated circuit device.

摘要翻译： 描述形成铜互连的方法。 该方法可以用于形成单镶嵌或双镶嵌互连。 向常规阻挡层添加铝阻挡层产生对铜扩散的优异屏障。 提供基底层。 沉积在基底层上的电介质层。 图案化的电介质层形成互连沟槽。 可以沉积可选的钛粘合层。 覆盖在沟槽的内表面上的铝阻挡层被沉积。 包含例如钛和氮化钛的第二阻挡层沉积在铝阻挡层上。 沉积铜层，覆盖第二阻挡层并填充互连沟槽。 铜层，第二阻挡层和铝阻挡层被抛光到介电层的顶表面以限定铜互连，并且完成集成电路器件的制造。

公开(公告)号：US06656643B2

公开(公告)日：2003-12-02

申请号：US09785116

申请日：2001-02-20

申请人： Subhash Gupta ,  Mei Sheng Zhou

发明人： Subhash Gupta ,  Mei Sheng Zhou

IPC分类号： G03F900

CPC分类号： B82Y10/00 ,  B82Y40/00 ,  G03F1/24 ,  G03F1/54

摘要： An EUV photolithographic mask device and a method of fabricating the same. The EUV photolithographic mask comprises a multi-layer over an EUV masking substrate and a patterned light absorbing layer formed on the multi-layer. The method comprises the steps of forming a multi-layer on an EUV mask substrate, forming a light absorbing layer on the multi-layer, and etching an opening through the light absorbing layer to the multi-layer. The light absorbing layer includes a metal selected from the group comprising nickel, chromium, cobalt, and alloys thereof, and is preferably nickel.

公开(公告)号：US06274499B1

公开(公告)日：2001-08-14

申请号：US09442493

申请日：1999-11-19

申请人： Subhash Gupta ,  Paul Kwok Keung Ho ,  Mei Sheng Zhou ,  Ramasamy Chockalingam

发明人： Subhash Gupta ,  Paul Kwok Keung Ho ,  Mei Sheng Zhou ,  Ramasamy Chockalingam

IPC分类号： H01L21302

CPC分类号： H01L21/76801 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/76807 ,  H01L21/76834

摘要： In accordance with the objects of this invention a new method to prevent copper contamination of the intermetal dielectric layer during etching, CMP, or post-etching and post-CMP cleaning by forming a dielectric cap for isolation of the underlying dielectric layer is described. In one embodiment of the invention, a dielectric layer is provided overlying a semiconductor substrate. A dielectric cap layer is deposited overlying the dielectric layer. A via is patterned and filled with a metal layer and planarized. A copper layer is deposited overlying the planarized metal layer and dielectric cap layer. The copper layer is etched to form a copper line wherein the dielectric cap layer prevents copper contamination of the dielectric layer during etching and cleaning. In another embodiment of the invention, a dielectric layer is provided overlying a semiconductor substrate. A dielectric cap layer is deposited overlying the dielectric layer. A dual damascene opening is formed through the dielectric cap layer and the dielectric layer. A copper layer is deposited overlying a barrier metal layer over the dielectric cap layer and filling the dual damascene opening. The copper layer is polished back to leave the copper layer only within the dual damascene opening where the dielectric cap layer prevents copper contamination of the dielectric layer during polishing and cleaning.

摘要翻译： 根据本发明的目的，描述了通过形成用于隔离下面介电层的电介质盖，在蚀刻，CMP或后蚀刻和后CMP清洗中防止金属间电介质层的铜污染的新方法。 在本发明的一个实施例中，提供覆盖在半导体衬底上的电介质层。 介电覆盖层沉积在介电层上。 通孔被图案化并填充有金属层并且被平坦化。 沉积在平坦化的金属层和电介质盖层上的铜层。 铜层被蚀刻以形成铜线，其中电介质盖层在蚀刻和清洁期间防止电介质层的铜污染。 在本发明的另一个实施例中，提供覆盖半导体衬底的电介质层。 介电覆盖层沉积在介电层上。 通过电介质盖层和电介质层形成双镶嵌开口。 将铜层沉积在电介质盖层上方的阻挡金属层上，并填充双镶嵌开口。 将铜层抛光回来，仅在双镶嵌开口中留下铜层，其中介电盖层在抛光和清洁期间防止电介质层的铜污染。

公开(公告)号：US06251786B1

公开(公告)日：2001-06-26

申请号：US09390783

申请日：1999-09-07

申请人： Mei Sheng Zhou ,  Paul Kwok Keung Ho ,  Subhash Gupta

发明人： Mei Sheng Zhou ,  Paul Kwok Keung Ho ,  Subhash Gupta

IPC分类号： H01L2100

CPC分类号： H01L21/76834 ,  H01L21/3212 ,  H01L21/76807 ,  H01L21/7684 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A dual damascene structure is created in a dielectric layer, the structure contains a barrier layer while a cap layer may or may not be provided over the layer of dielectric for further protection of the dual damascene structure. The surface of the copper in the dual damascene structure is recessed, a thin film is deposited and planarized/partially removed by either CMP or a plasma etch thereby providing a sturdy surface above the copper of the dual damascene structure that prevents dishing and erosion of this surface.

摘要翻译： 在电介质层中产生双镶嵌结构，该结构包含阻挡层，而覆盖层可以设置在电介质层上，也可以不设置在电介质层上，以进一步保护双镶嵌结构。 双镶嵌结构中的铜的表面是凹进的，通过CMP或等离子体蚀刻沉积并平面化/部分去除薄膜，从而在双镶嵌结构的铜上方提供坚固的表面，防止该镶嵌结构的凹陷和侵蚀 表面。

公开(公告)号：US06184138B2

公开(公告)日：2001-02-06

申请号：US09390782

申请日：1999-09-07

申请人： Paul Kwok Keung Ho ,  Mei Sheng Zhou ,  Subhash Gupta

发明人： Paul Kwok Keung Ho ,  Mei Sheng Zhou ,  Subhash Gupta

IPC分类号： H01L2144

CPC分类号： H01L21/76843 ,  H01L21/7684 ,  H01L21/76874 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879

摘要： A new method is provided to construct a copper dual damascene structure. A layer of IMD is deposited over the surface of a substrate. A cap layer is deposited over this layer of IMD, the dual damascene structure is then patterned through the cap layer and into the layer of IMD. A barrier layer is blanket deposited, a copper seed layer is deposited over the barrier layer. The dual damascene structure is then filled with a spin-on material. The barrier layer and the copper seed layer are removed above the cap layer; the cap layer can be partially removed or can be left in place. The spin on material remains in place in the via and trench opening during the operation of removing the copper seed layer and the barrier layer from above the cap surface thereby protecting the inside surfaces of these openings. The spin-on material is next removed from the dual damascene structure and copper is deposited. The cap layer that is still present above the surface of the IMD protects the dielectric from being contaminated with copper solution during the deposition of the copper. The excess copper is removed using a touch-up CMP. The cap layer over the surface of the IMD can, after the copper has been deposited, be removed if this is so desired. As a final step in the process, a liner or oxidation/diffusion protection layer is deposited over the dual damascene structure and its surrounding area.

摘要翻译： 提供了一种构建铜双镶嵌结构的新方法。 一层IMD沉积在衬底的表面上。 覆盖层沉积在IMD的该层上，然后将双镶嵌结构通过盖层图案化并进入IMD层。 阻挡层被覆盖沉积，铜晶种层沉积在阻挡层上。 然后用镶嵌材料填充双镶嵌结构。 在盖层上除去阻挡层和铜籽晶层; 盖层可以被部分地去除或可以留在原处。 在从盖表面上方去除铜种子层和阻挡层的操作期间，材料上的旋转保持在通孔和沟槽开口中的适当位置，从而保护这些开口的内表面。 随后从双镶嵌结构中去除旋涂材料，并沉积铜。 仍然存在于IMD表面之上的盖层保护铜在沉积期间不被铜溶液污染。 使用上层CMP去除多余的铜。 如果这样做是希望的话，在沉积铜之后，IMD表面上的盖层可以被去除。 作为该方法的最后一步，衬垫或氧化/扩散保护层沉积在双镶嵌结构及其周围区域上。