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    BULK FINFET WITH CONTROLLED FIN HEIGHT AND HIGH-K LINER
    41.
    发明申请
    BULK FINFET WITH CONTROLLED FIN HEIGHT AND HIGH-K LINER 有权
    具有控制高度和高K内衬的大容量FINFET

    公开(公告)号：US20140061820A1

    公开(公告)日：2014-03-06

    申请号：US13604658

    申请日：2012-09-06

    申请人： Alexander Reznicek ,  Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz

    发明人： Alexander Reznicek ,  Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz

    IPC分类号： H01L21/336 ,  H01L27/088

    CPC分类号： H01L29/785 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0684 ,  H01L29/1054 ,  H01L29/66795

    摘要： A method of forming a semiconductor device that includes forming a material stack on a semiconductor substrate, the material stack including a first dielectric layer on the substrate, a second dielectric layer on the first dielectric layer, and a third dielectric layer on the second dielectric layer, wherein the second dielectric layer is a high-k dielectric. Openings are formed through the material stack to expose a surface of the semiconductor substrate. A semiconductor material is formed in the openings through the material stack. The first dielectric layer is removed selectively to the second dielectric layer and the semiconductor material. A gate structure is formed on a channel portion of the semiconductor material. In some embodiments, the method may provide a plurality of finFET or trigate semiconductor device in which the fin structures of those devices have substantially the same height.

    摘要翻译： 一种形成半导体器件的方法，包括在半导体衬底上形成材料堆叠，所述材料堆叠包括在所述衬底上的第一介电层，所述第一电介质层上的第二电介质层和所述第二电介质层上的第三电介质层 ，其中所述第二电介质层是高k电介质。 通过材料堆叠形成开口以暴露半导体衬底的表面。 通过材料堆叠在开口中形成半导体材料。 第一电介质层被选择性地去除到第二电介质层和半导体材料。 栅极结构形成在半导体材料的沟道部分上。 在一些实施例中，该方法可以提供多个finFET或者触发半导体器件，其中这些器件的鳍结构具有基本上相同的高度。

    Selectively raised source/drain transistor
    43.
    发明授权
    Selectively raised source/drain transistor 有权
    选择性地升高源极/漏极晶体管

    公开(公告)号：US08592916B2

    公开(公告)日：2013-11-26

    申请号：US13424787

    申请日：2012-03-20

    申请人： Ali Khakifirooz ,  Thomas N. Adam ,  Kangguo Cheng ,  Alexander Reznicek

    发明人： Ali Khakifirooz ,  Thomas N. Adam ,  Kangguo Cheng ,  Alexander Reznicek

    IPC分类号： H01L21/02

    CPC分类号： H01L27/088 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/41791 ,  H01L29/66628 ,  H01L29/7834

    摘要： A lower raised source/drain region is formed on a planar source/drain region of a planar field effect transistor or a surface of a portion of semiconductor fin adjoining a channel region of a fin field effect transistor. At least one contact-level dielectric material layer is formed and planarized, and a contact via hole extending to the lower raised source/drain region is formed in the at least one contact-level dielectric material layer. An upper raised source/drain region is formed on a top surface of the lower raised source/drain region. A metal semiconductor alloy portion and a contact via structure are formed within the contact via hole. Formation of the upper raised source/drain region is limited to a bottom portion of the contact via hole, thereby preventing formation of, and increase of parasitic capacitance by, any additional raised structure in source/drain regions that are not contacted.

    摘要翻译： 在平面场效应晶体管的平面源极/漏极区域或与鳍状场效应晶体管的沟道区域相邻的半导体鳍片的一部分的表面上形成下部凸起的源极/漏极区域。 形成并平坦化至少一个接触层介电材料层，并且在该至少一个接触层电介质材料层中形成延伸到下凸起源/漏区的接触通孔。 上凸起的源/漏区形成在下凸起的源/漏区的顶表面上。 在接触通孔内形成金属半导体合金部分和接触通孔结构。 上部隆起源极/漏极区域的形成被限制在接触通孔的底部，从而通过未被接触的源极/漏极区域中的任何额外的凸起结构来防止寄生电容的形成和增加。

    METHOD FOR FORMING SEMICONDUCTOR DEVICE WITH EPITAXY SOURCE AND DRAIN REGIONS INDEPENDENT OF PATTERNING AND LOADING
    44.
    发明申请
    METHOD FOR FORMING SEMICONDUCTOR DEVICE WITH EPITAXY SOURCE AND DRAIN REGIONS INDEPENDENT OF PATTERNING AND LOADING 审中-公开
    用于形成具有外来源和排水区的半导体器件的方法，独立于填充和加载

    公开(公告)号：US20130270560A1

    公开(公告)日：2013-10-17

    申请号：US13448876

    申请日：2012-04-17

    申请人： Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Yu Zhu ,  Thomas N. Adam

    发明人： Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Yu Zhu ,  Thomas N. Adam

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/785 ,  H01L29/66795

    摘要： A method of fabricating a semiconductor device that includes providing a gate structure on a channel portion of a semiconductor on insulator (SOI) layer of a semiconductor on insulator (SOI) substrate, and forming an amorphous semiconductor layer on at least a source region portion and a drain region portion of the SOI layer. The amorphous semiconductor layer is converted to a crystalline semiconductor material, wherein the crystalline semiconductor material provides a raised source region and a raised drain region of the semiconductor device. The method may be applicable to planar semiconductor devices and finFET semiconductor devices.

    摘要翻译： 一种制造半导体器件的方法，包括在绝缘体上半导体（SOI）衬底上的半导体绝缘体（SOI）层的沟道部分上提供栅极结构，并且在至少源极区部分上形成非晶半导体层，以及 SOI层的漏极区域部分。 将非晶半导体层转换为晶体半导体材料，其中晶体半导体材料提供半导体器件的升高的源极区域和升高的漏极区域。 该方法可以应用于平面半导体器件和finFET半导体器件。

    THIN HETEREOSTRUCTURE CHANNEL DEVICE
    45.
    发明申请
    THIN HETEREOSTRUCTURE CHANNEL DEVICE 有权
    薄型结构通道设备

    公开(公告)号：US20130161693A1

    公开(公告)日：2013-06-27

    申请号：US13336251

    申请日：2011-12-23

    申请人： Thomas N. Adam ,  Kangguo Cheng ,  Hong He ,  Ali Khakifirooz ,  Alexander Reznicek

    发明人： Thomas N. Adam ,  Kangguo Cheng ,  Hong He ,  Ali Khakifirooz ,  Alexander Reznicek

    IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L21/336

    CPC分类号： H01L21/02057 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/3065 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/1054

    摘要： A method of fabricating a semiconductor device that includes providing a substrate having at least a first semiconductor layer atop a dielectric layer, wherein the first semiconductor layer has a first thickness of less than 10 nm. The first semiconductor layer is etched with a a halide based gas at a temperature of less than 675° C. to a second thickness that is less than the first thickness. A second semiconductor layer is epitaxially formed on an etched surface of the first semiconductor layer. A gate structure is formed directly on the second semiconductor layer. A source region and a drain region is formed on opposing sides of the gate structure.

    摘要翻译： 一种制造半导体器件的方法，其包括提供在电介质层顶部具有至少第一半导体层的衬底，其中所述第一半导体层具有小于10nm的第一厚度。 在小于675℃的温度下用卤化物基气体蚀刻第一半导体层至小于第一厚度的第二厚度。 在第一半导体层的蚀刻表面上外延形成第二半导体层。 栅极结构直接形成在第二半导体层上。 源极区域和漏极区域形成在栅极结构的相对侧上。

    THIN BODY SEMICONDUCTOR DEVICES
    48.
    发明申请
    THIN BODY SEMICONDUCTOR DEVICES 有权
    薄体半导体器件

    公开(公告)号：US20110263104A1

    公开(公告)日：2011-10-27

    申请号：US12766859

    申请日：2010-04-24

    申请人： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

    发明人： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

    IPC分类号： H01L21/20

    CPC分类号： H01L29/66628 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/78696

    摘要： A method for fabricating an FET device is disclosed. The method includes providing a body over an insulator, with the body having at least one surface adapted to host a device channel. Selecting the body to be Si, Ge, or their alloy mixtures. Choosing the body layer to be less than a critical thickness defined as the thickness where agglomeration may set in during a high temperature processing. Such critical thickness may be about 4 nm for a planar devices, and about 8 nm for a non-planar devices. The method further includes clearing surfaces of oxygen at low temperature, and forming a raised source/drain by selective epitaxy while using the cleared surfaces for seeding. After the clearing of the surfaces of oxygen, and before the selective epitaxy, oxygen exposure of the cleared surfaces is being prevented.

    摘要翻译： 公开了一种用于制造FET器件的方法。 该方法包括在绝缘体上提供主体，其中主体具有适于承载设备通道的至少一个表面。 选择身体为Si，Ge或其合金混合物。 选择体层小于临界厚度，其临界厚度定义为在高温加工过程中聚集的厚度。 这种临界厚度对于平面器件可以是约4nm，对于非平面器件而言约8nm。 该方法还包括在低温下清除氧的表面，并且通过选择性外延形成凸起的源极/漏极，同时使用清除的表面进行接种。 在氧的表面清除之后，并且在选择性外延之前，防止了清除的表面的氧曝光。

    Field effect transistor device with raised active regions
    50.
    发明授权
    Field effect transistor device with raised active regions 有权
    场效应晶体管器件具有凸起的有源区

    公开(公告)号：US08445971B2

    公开(公告)日：2013-05-21

    申请号：US13237319

    申请日：2011-09-20

    申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek

    发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek

    IPC分类号： H01L29/76 ,  H01L31/062

    CPC分类号： H01L29/41783 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78654

    摘要： A method for fabricating a field effect transistor device includes forming a gate stack on a substrate, forming a spacer on the substrate, adjacent to the gate stack, forming a first portion of an active region on the substrate, the first portion of the active region having a first facet surface adjacent to the gate stack, forming a second portion of the active region on a portion of the first portion of the active region, the second portion of the active region having a second facet surface adjacent to the gate stack, the first facet surface and the second facet surface partially defining a cavity adjacent to the gate stack.

    摘要翻译： 一种用于制造场效应晶体管器件的方法，包括在衬底上形成栅极叠层，在衬底上邻近栅堆叠形成间隔物，在衬底上形成有源区的第一部分，有源区的第一部分 具有邻近所述栅叠层的第一刻面，在所述有源区的所述第一部分的一部分上形成所述有源区的第二部分，所述有源区的所述第二部分具有邻近所述栅叠层的第二刻面， 第一小面表面和第二小面表面部分地限定与栅极叠层相邻的空腔。