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    Epitaxial semiconductor resistor with semiconductor structures on same substrate
    2.
    发明授权
    Epitaxial semiconductor resistor with semiconductor structures on same substrate 有权
    外延半导体电阻，半导体结构在同一基板上

    公开(公告)号：US08956938B2

    公开(公告)日：2015-02-17

    申请号：US13472747

    申请日：2012-05-16

    申请人： Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Thomas N. Adam

    发明人： Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Thomas N. Adam

    IPC分类号： H01L21/336 ,  H01L27/088

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/13 ,  H01L28/20 ,  H01L29/0649 ,  H01L29/36 ,  H01L29/41783

    摘要： An electrical device is provided that includes a substrate having an upper semiconductor layer, a buried dielectric layer and a base semiconductor layer. At least one isolation region is present in the substrate that defines a semiconductor device region and a resistor device region. The semiconductor device region includes a semiconductor device having a back gate structure that is present in the base semiconductor layer. Electrical contact to the back gate structure is provided by doped epitaxial semiconductor pillars that extend through the buried dielectric layer. An epitaxial semiconductor resistor is present in the resistor device region. Undoped epitaxial semiconductor pillars extending from the epitaxial semiconductor resistor to the base semiconductor layer provide a pathway for heat generated by the epitaxial semiconductor resistor to be dissipated to the base semiconductor layer. The undoped and doped epitaxial semiconductor pillars are composed of the same epitaxial semiconductor material.

    摘要翻译： 提供了一种电气装置，其包括具有上半导体层，埋入介质层和基底半导体层的衬底。 衬底中存在至少一个限定半导体器件区域和电阻器器件区域的隔离区域。 半导体器件区域包括具有存在于基极半导体层中的背栅极结构的半导体器件。 与背栅结构的电接触由穿过掩埋介电层的掺杂的外延半导体柱提供。 外延半导体电阻存在于电阻器件区域中。 从外延半导体电阻器延伸到基底半导体层的未掺杂的外延半导体柱提供了由外延半导体电阻器产生的用于散发到基极半导体层的热通路。 未掺杂和掺杂的外延半导体柱由相同的外延半导体材料组成。

    FinFET with enhanced embedded stressor
    3.
    发明授权
    FinFET with enhanced embedded stressor 有权
    FinFET具有增强的嵌入式压力

    公开(公告)号：US08853750B2

    公开(公告)日：2014-10-07

    申请号：US13457529

    申请日：2012-04-27

    申请人： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek

    发明人： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek

    IPC分类号： H01L29/76

    CPC分类号： H01L29/66795 ,  H01L21/26506 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/36 ,  H01L29/7848 ,  H01L29/7851

    摘要： A channel region of a finFET has fins having apexes in a first direction parallel to a surface of a substrate, each fin extending downwardly from the apex, with a gate overlying the apexes and between adjacent fins. A semiconductor stressor region extends in at least the first direction away from the fins to apply a stress to the channel region. Source and drain regions of the finFET can be separated from one another by the channel region, with the source and/or drain at least partly in the semiconductor stressor region. The stressor region includes a first semiconductor region and a second semiconductor region overlying and extending from the first semiconductor region. The second semiconductor region can be more heavily doped than the first semiconductor region, and the first and second semiconductor regions can have opposite conductivity types where at least a portion of the second semiconductor region meets the first semiconductor region.

    摘要翻译： finFET的沟道区域具有鳍片，鳍片具有平行于衬底表面的第一方向的顶点，每个鳍片从顶点向下延伸，栅极覆盖顶点和相邻鳍片之间。 半导体应力区域至少沿着第一方向延伸离开翅片，以对通道区域施加应力。 鳍状物FET的源极和漏极区域可以通过沟道区域彼此分离，源极和/或漏极至少部分地在半导体应力区域中。 应力区域包括覆盖并从第一半导体区域延伸的第一半导体区域和第二半导体区域。 第二半导体区域可以比第一半导体区域更重掺杂，并且第一和第二半导体区域可以具有相反的导电类型，其中第二半导体区域的至少一部分与第一半导体区域相交。

    Bulk finFET with controlled fin height and high-K liner
    4.
    发明授权
    Bulk finFET with controlled fin height and high-K liner 有权
    散装finFET具有可控翅片高度和高K衬垫

    公开(公告)号：US08841188B2

    公开(公告)日：2014-09-23

    申请号：US13604658

    申请日：2012-09-06

    申请人： Alexander Reznicek ,  Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz

    发明人： Alexander Reznicek ,  Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz

    IPC分类号： H01L21/336

    CPC分类号： H01L29/785 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0684 ,  H01L29/1054 ,  H01L29/66795

    摘要： A method of forming a semiconductor device that includes forming a material stack on a semiconductor substrate, the material stack including a first dielectric layer on the substrate, a second dielectric layer on the first dielectric layer, and a third dielectric layer on the second dielectric layer, wherein the second dielectric layer is a high-k dielectric. Openings are formed through the material stack to expose a surface of the semiconductor substrate. A semiconductor material is formed in the openings through the material stack. The first dielectric layer is removed selectively to the second dielectric layer and the semiconductor material. A gate structure is formed on a channel portion of the semiconductor material. In some embodiments, the method may provide a plurality of finFET or trigate semiconductor device in which the fin structures of those devices have substantially the same height.

    摘要翻译： 一种形成半导体器件的方法，包括在半导体衬底上形成材料堆叠，所述材料堆叠包括在所述衬底上的第一介电层，所述第一电介质层上的第二电介质层和所述第二电介质层上的第三电介质层 ，其中所述第二电介质层是高k电介质。 通过材料堆叠形成开口以暴露半导体衬底的表面。 通过材料堆叠在开口中形成半导体材料。 第一电介质层被选择性地去除到第二电介质层和半导体材料。 栅极结构形成在半导体材料的沟道部分上。 在一些实施例中，该方法可以提供多个finFET或者触发半导体器件，其中这些器件的鳍结构具有基本上相同的高度。

    SEMICONDUCTOR DEVICES HAVING FIN STRUCTURES, AND METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING FIN STRUCTURES
    7.
    发明申请
    SEMICONDUCTOR DEVICES HAVING FIN STRUCTURES, AND METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING FIN STRUCTURES 有权
    具有精细结构的半导体器件，以及形成具有结构的半导体器件的方法

    公开(公告)号：US20130270655A1

    公开(公告)日：2013-10-17

    申请号：US13448749

    申请日：2012-04-17

    申请人： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek

    发明人： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek

    IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/20

    CPC分类号： H01L29/78 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/20 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

    摘要： A semiconductor device including at least two fin structures on a substrate surface and a functional gate structure present on the at least two fin structures. The functional gate structure includes at least one gate dielectric that is in direct contact with at least the sidewalls of the two fin structures, and at least one gate conductor on the at least one gate dielectric. The sidewall of the gate structure is substantially perpendicular to the upper surface of the substrate surface, wherein the plane defined by the sidewall of the gate structure and a plane defined by an upper surface of the substrate surface intersect at an angle of 90°+/−5°. An epitaxial semiconductor material is in direct contact with the at least two fin structures.

    摘要翻译： 一种半导体器件，包括在衬底表面上的至少两个鳍结构和存在于所述至少两个鳍结构上的功能栅结构。 功能栅极结构包括至少一个与至少两个鳍结构的侧壁直接接触的栅极电介质，以及至少一个栅极电介质上的至少一个栅极导体。 栅极结构的侧壁基本上垂直于衬底表面的上表面，其中由栅极结构的侧壁限定的平面和由衬底表面的上表面限定的平面以90°±/ -5°。 外延半导体材料与至少两个翅片结构直接接触。

    STRAINED SOI FINFET ON EPITAXIALLY GROWN BOX
    8.
    发明申请
    STRAINED SOI FINFET ON EPITAXIALLY GROWN BOX 审中-公开
    外延生长框架上的应变SOI结构

    公开(公告)号：US20130270638A1

    公开(公告)日：2013-10-17

    申请号：US13445959

    申请日：2012-04-13

    申请人： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan

    发明人： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/785 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848

    摘要： A semiconductor structure includes an epitaxial insulator layer located on a substrate. A fin structure is located on the epitaxial insulator layer, where at least one epitaxial source-drain region having an embedded stressor is located on the epitaxial insulator layer and abuts at least one sidewall associated with the fin structure. The epitaxial source-drain region having the embedded stressor provides stress along the fin structure such that the provided stress is based on a lattice mismatch between the epitaxial source-drain region, and both the epitaxial insulator layer and the one side-wall associated with the fin structure.

    摘要翻译： 半导体结构包括位于衬底上的外延绝缘体层。 翅片结构位于外延绝缘体层上，其中具有嵌入的应力源的至少一个外延源极 - 漏极区域位于外延绝缘体层上并邻接与翅片结构相关联的至少一个侧壁。 具有嵌入的应力源的外延源极 - 漏极区域沿着鳍状结构提供应力，使得所提供的应力基于外延源极 - 漏极区域和外延绝缘体层与与该外部源极 - 漏极区域相关联的一个侧壁之间的晶格失配 翅片结构。