公开(公告)号：US20090091406A1

公开(公告)日：2009-04-09

申请号：US12249273

申请日：2008-10-10

申请人： Taras KUSHTA ,  Kaoru Narita ,  Takanori Saeki ,  Tomoyuki Kaneko ,  Hirokazu Tohya

发明人： Taras KUSHTA ,  Kaoru Narita ,  Takanori Saeki ,  Tomoyuki Kaneko ,  Hirokazu Tohya

IPC分类号： H01P1/00

CPC分类号： H05K1/0222 ,  H01P3/06 ,  H05K1/024 ,  H05K1/0251 ,  H05K3/429 ,  H05K2201/0187 ,  H05K2201/09063 ,  H05K2201/09536 ,  H05K2201/09618 ,  H05K2201/09718 ,  H05K2201/09809

摘要： A compact via transmission line for a printed circuit board having preferred characteristic impedance and capable of miniaturizing the printed circuit board including a multilayer printed circuit board, and extending the frequency range of a via transmission line mounted on the printed circuit board, and a design method of the same. The transmission line has a central conductor forming an inner conductor layer boundary make up a signal via hole, a plurality of via holes arranged around the central conductor form an outer conductor layer boundary, and a plurality of conductor plates formed of a printed circuit board conductor layer, is further provided with a constitutive parameter adjustment clearance hole between the inner and outer conductor layer boundaries of the compact via transmission line, and electrically isolates to prevent cross-talk of a signal propagating through a signal via hole with other signals in a high-frequency signal band.

摘要翻译： 一种用于具有优选特性阻抗并能够使包括多层印刷电路板的印刷电路板小型化并且扩展安装在印刷电路板上的通孔传输线的频率范围的印刷电路板的紧凑型通路传输线，以及设计方法 一样的。 传输线具有形成内导体层边界的中心导体，构成信号通孔，围绕中心导体布置的多个通孔形成外导体层边界，以及由印刷电路板导体形成的多个导体板 通过传输线在压缩体的内部和外部导体层边界之间进一步设置本构参数调整间隙孔，并且电隔离以防止通过信号通孔传播的信号与其他信号在高电平中的串扰 频率信号频带。

公开(公告)号：US20070205847A1

公开(公告)日：2007-09-06

申请号：US10598134

申请日：2005-03-09

申请人： Taras Kushta ,  Kaoru Narita ,  Hirokazu Tohya ,  Takanori Saeki ,  Tomoyuki Kaneko

发明人： Taras Kushta ,  Kaoru Narita ,  Hirokazu Tohya ,  Takanori Saeki ,  Tomoyuki Kaneko

IPC分类号： H01P5/02

CPC分类号： H05K1/0222 ,  H05K1/0269 ,  H05K3/429 ,  H05K2201/09536 ,  H05K2201/09618 ,  H05K2201/09718 ,  H05K2201/09809

摘要： A via transmission line for a multilayer printed circuit board (PCB) in which a wave guiding channel is formed by a signal via or a number of signal vias, an assembly of ground vias surrounding the signal via or corresponding number of coupled signal vias, a set of ground plates from conductor layers of the multilayer PCB, and a clearance hole. In this via transmission line, the signal via, or the number of signal vias forms an inner conductive boundary, ground vias and ground plates from conductor layers of the multilayer PCB form an outer conductive boundary, and the clearance hole provides both isolation of the inner conductive boundary from the outer conductive boundary and high-performance broadband operation of the via transmission line by means of the predetermined clearance hole cross-sectional shape and dimensions where the cross-sectional shape of the clearance hole is defined by the arrangement of ground vias in the outer conductive boundary and dimensions of the clearance hole are determined according to a method to minimize frequency-dependent return losses caused by specific corrugations of the outer conductive boundary formed by ground plates in the wave guiding channel of the via transmission line.

摘要翻译： 一种用于多层印刷电路板（PCB）的通孔传输线，其中通过信号通道或多个信号通路形成波导通道，围绕信号通孔或相应数量的耦合信号通孔的接地通孔的组件， 多层PCB的导体层的接地板组以及间隙孔。 在这个通过传输线路中，信号通孔或信号通道的数量形成内部导电边界，从多层PCB的导体层形成的接地孔和接地板形成外部导电边界，并且间隙孔提供内部 通过外部导电边界的导电边界和通孔传输线的高性能宽带操作，借助于预定的间隙孔横截面形状和尺寸，其中间隙孔的横截面形状由接地通孔的布置 根据通过在通孔传输线的波导通道中由接地板形成的外导电边界的特定波纹引起的频率相关的返回损耗的方法来确定间隙孔的外导电边界和尺寸。

公开(公告)号：US06433393B1

公开(公告)日：2002-08-13

申请号：US09659067

申请日：2000-09-11

申请人： Kaoru Narita

发明人： Kaoru Narita

IPC分类号： H01L2362

CPC分类号： H01L27/0262 ,  H01L29/7436 ,  H01L29/87 ,  H01L2924/0002 ,  H01L2924/00

摘要： The distance between an anode and a cathode of a thyristor and the anode and the cathode of a diode formed in a semiconductor protective circuit are made a small as allowable by LSI manufacturing technology, thereby achieving fast starting speed and a low internal resistance when in the conducting condition, so as to limit the rise in voltage on an internal circuit, even when a high-speed pulse is applied.

摘要翻译： 晶闸管的阳极和阴极之间的距离以及形成在半导体保护电路中的二极管的阳极和阴极之间的距离被制造为通过LSI制造技术允许的小，从而当在...的制造技术中实现快速启动速度和低内阻 导通条件，即使施加高速脉冲也能够限制内部电路的电压上升。

公开(公告)号：US6081013A

公开(公告)日：2000-06-27

申请号：US159788

申请日：1998-09-24

申请人： Kaoru Narita

发明人： Kaoru Narita

IPC分类号： H01L21/822 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/04 ,  H01L27/088 ,  H01L29/78 ,  H01L23/62

CPC分类号： H01L27/0251

摘要： In a semiconductor device including a semiconductor substrate, first and second external terminals, a first impurity diffusion region connected to the first external terminal, and second and third impurity diffusion regions forming a MIS transistor, one of the second and third impurity diffusion regions facing the first impurity region is connected to the second external terminal. The distance between the first diffusion region and the MIS transistor is substantially smaller than a certain value compared to conventional devices.

摘要翻译： 在包括半导体衬底，第一和第二外部端子的半导体器件中，连接到第一外部端子的第一杂质扩散区域和形成MIS晶体管的第二和第三杂质扩散区域，第二和第三杂质扩散区域中的一个面向 第一杂质区连接到第二外部端子。 与常规器件相比，第一扩散区域和MIS晶体管之间的距离显着小于特定值。

公开(公告)号：US5953191A

公开(公告)日：1999-09-14

申请号：US16636

申请日：1998-01-30

申请人： Kaoru Narita

发明人： Kaoru Narita

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H02H9/00

CPC分类号： H01L27/0248 ,  H01L2924/0002

摘要： Voltage clamping elements are respectively paired with first diodes, and the pairs of voltage clamping elements/first diodes are connected between a first common discharge line and power terminals selectively supplied with positive power voltage and ground voltage; however, the pairs of voltage clamping elements/first diodes can not prevent an internal circuit from excess voltage if a positive electrostatic pulse with respect to the positive power voltage is applied to the ground terminal; second diodes are connected between a second common discharge line and the terminals in such a manner as to discharge the positive electrostatic pulse through the associated forward-biased second diodes, and the internal circuit is perfectly prevented from the excess voltage.

摘要翻译： 电压钳位元件分别与第一二极管配对，并且成对的电压钳位元件/第一二极管连接在第一公共放电线路和选择性地提供正电源电压和接地电压的电源端子之间; 然而，如果对接地端子施加相对于正电源电压的正静电脉冲，则成对的电压钳位元件/第一二极管不能防止内部电路过剩电压; 第二二极管以这样的方式连接在第二公共放电线和端子之间，以便通过相关联的正向偏置的第二二极管放电正静电脉冲，并且内部电路被完全防止过电压。

公开(公告)号：US5844281A

公开(公告)日：1998-12-01

申请号：US585864

申请日：1996-01-11

申请人： Kaoru Narita

发明人： Kaoru Narita

IPC分类号： H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/04 ,  H01L27/088 ,  H01L27/092 ,  H01L23/62

CPC分类号： H01L27/0288 ,  H01L2924/0002

摘要： An input terminal and an input protective resistor of an N-type diffusion layer connected thereto are provided on a P-type semiconductor substrate. First and second N-type MOS transistors for internal circuit are connected to a grounding wiring at respective source diffusion layers. The first MOS transistor is located at closer distance from the input protective resister than the second MOS transistor. The source diffusion layer of the first MOS transistor and the grounding wiring are connected via a high melting point metal layer wiring, such as a tungsten silicide or so forth to increase a resistance to improve electrostatic breakdown potential. Accordingly, the distance between the input protective resistor and the first MOS transistor can be made smaller to eliminate dead space around the input protective resistor to enable reduction of a chip area.

摘要翻译： 在P型半导体衬底上设置有与其连接的N型扩散层的输入端子和输入保护电阻。 用于内部电路的第一和第二N型MOS晶体管连接到各个源极扩散层处的接地布线。 第一MOS晶体管位于比第二MOS晶体管更靠近输入保护电阻的距离处。 第一MOS晶体管的源极扩散层和接地布线经由诸如硅化钨等的高熔点金属层布线连接，以增加电阻以提高静电击穿电位。 因此，可以使输入保护电阻和第一MOS晶体管之间的距离更小，以消除输入保护电阻周围的死区，以减少芯片面积。

公开(公告)号：US5710452A

公开(公告)日：1998-01-20

申请号：US627093

申请日：1996-04-03

申请人： Kaoru Narita

发明人： Kaoru Narita

IPC分类号： H01L29/78 ,  H01L27/02 ,  H01L27/06 ,  H01L23/62

CPC分类号： H01L27/0259

摘要： A semiconductor device includes a metallic main line connected between an external terminal and an internal circuit, and a plurality of divided protection bipolar transistors connected in parallel to one another. Each of the divided protection bipolar transistors includes a collector and an emitter composed of first and second N diffused regions formed in a semiconductor substrate which are separated from each other. Each of the divided protection bipolar transistors also includes a base formed of a portion of a semiconductor substrate between the collector and the emitter. The collector is connected to a metallic sub line branched from the main line, and the emitter is connected to ground. The plurality of divided protection bipolar transistors have an equal breakdown voltage between the collector of the divided protection bipolar transistor and the semiconductor substrate. Thus, the protection device composed of a plurality of divided protection bipolar transistors connected in parallel to one another can effectively protect the internal circuit from a short electrostatic pulse.

摘要翻译： 半导体器件包括连接在外部端子和内部电路之间的金属主线以及彼此并联连接的多个分开的保护双极型晶体管。 每个分压保护双极型晶体管包括集电极和由形成在半导体衬底中的彼此分离的第一和第二N个扩散区组成的发射极。 每个分压保护双极晶体管还包括由集电极和发射极之间的半导体衬底的一部分形成的基极。 集电极连接到从主线分支的金属副线，并且发射极连接到地。 多个分压保护双极晶体管在分压保护双极晶体管的集电极和半导体衬底之间具有相等的击穿电压。 因此，由彼此并联连接的多个分割保护双极晶体管组成的保护装置可以有效地保护内部电路免受短静电脉冲的影响。

公开(公告)号：US5449939A

公开(公告)日：1995-09-12

申请号：US364275

申请日：1994-12-27

申请人： Yoko Horiguchi ,  Kaoru Narita

发明人： Yoko Horiguchi ,  Kaoru Narita

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L29/06 ,  H01L29/78

CPC分类号： H01L27/0259

摘要： A semiconductor device has an internal circuit, an output transistor and a protective transistor for protecting the output transistor and the internal circuit against an ESD-induced destruction caused by a surge pulse entering from an input/output terminal. The sum of a first distance between a contact for connecting an input/output terminal with the collector of the protective transistor and a field oxide film and a second distance between a contact for connecting the input/output terminal with the emitter of the protective transistor and the field oxide film overlying the base of the laterally formed protective transistor is made smaller than the sum of a third distance between a contact for connecting the input/output terminal with the drain of the output transistor and the gate electrode of the output transistor and a fourth distance between a contact for connecting a potential line with the source of the output transistor and the gate electrode of the output transistor. Besides, the effective channel length of the output transistor is made longer than the effective base width of the protective transistor.

摘要翻译： 半导体器件具有内部电路，输出晶体管和保护晶体管，用于保护输出晶体管和内部电路免受由输入/输出端子进入的浪涌脉冲引起的ESD引起的破坏。 用于将输入/输出端子与保护晶体管的集电极连接的触头与场氧化膜之间的第一距离与用于将输入/输出端子与保护晶体管的发射极连接的触点之间的第二距离之和，以及 使横向形成的保护晶体管的基部覆盖的场氧化膜小于用于将输入/输出端子与输出晶体管的漏极和输出晶体管的栅极连接的触点之间的第三距离和 用于将电位线与输出晶体管的源极和输出晶体管的栅电极连接的触点之间的第四距离。 此外，输出晶体管的有效沟道长度比保护晶体管的有效基极宽度长。