公开(公告)号：US07750765B2

公开(公告)日：2010-07-06

申请号：US12249273

申请日：2008-10-10

申请人： Taras Kushta ,  Kaoru Narita ,  Takanori Saeki ,  Tomoyuki Kaneko ,  Hirokazu Tohya

发明人： Taras Kushta ,  Kaoru Narita ,  Takanori Saeki ,  Tomoyuki Kaneko ,  Hirokazu Tohya

IPC分类号： H03H7/38 ,  H01P1/04

CPC分类号： H05K1/0222 ,  H01P3/06 ,  H05K1/024 ,  H05K1/0251 ,  H05K3/429 ,  H05K2201/0187 ,  H05K2201/09063 ,  H05K2201/09536 ,  H05K2201/09618 ,  H05K2201/09718 ,  H05K2201/09809

摘要： A compact via transmission line for a printed circuit board having preferred characteristic impedance and capable of miniaturizing the printed circuit board including a multilayer printed circuit board, and extending the frequency range of a via transmission line mounted on the printed circuit board, and a design method of the same. The transmission line has a central conductor forming an inner conductor layer boundary make up a signal via hole, a plurality of via holes arranged around the central conductor form an outer conductor layer boundary, and a plurality of conductor plates formed of a printed circuit board conductor layer, is further provided with a constitutive parameter adjustment clearance hole between the inner and outer conductor layer boundaries of the compact via transmission line, and electrically isolates to prevent cross-talk of a signal propagating through a signal via hole with other signals in a high-frequency signal band.

摘要翻译： 一种用于具有优选特性阻抗并能够使包括多层印刷电路板的印刷电路板小型化并且扩展安装在印刷电路板上的通孔传输线的频率范围的印刷电路板的紧凑型通路传输线，以及设计方法 一样的。 传输线具有形成内导体层边界的中心导体，构成信号通孔，围绕中心导体布置的多个通孔形成外导体层边界，以及由印刷电路板导体形成的多个导体板 通过传输线在压缩体的内部和外部导体层边界之间进一步设置本构参数调整间隙孔，并且电隔离以防止通过信号通孔传播的信号与其他信号在高电平中的串扰 频率信号频带。

公开(公告)号：US5910675A

公开(公告)日：1999-06-08

申请号：US763513

申请日：1996-12-11

申请人： Yoko Horiguchi ,  Kaoru Narita ,  Takeo Fujii

发明人： Yoko Horiguchi ,  Kaoru Narita ,  Takeo Fujii

IPC分类号： H01L27/02 ,  H01L27/06 ,  H01L29/72

CPC分类号： H01L27/0248 ,  H01L27/0635

摘要： A semiconductor device includes a metal terminal provided on a semiconductor substrate and a protection element. The protection element includes an insulated gate field-effect transistor. The transistor has a first diffusion layer of a reverse conductive-type formed on one conductive type region of the semiconductor substrate and connected to the metal terminal, as its source. The transistor also includes a second diffusion layer of a reverse conductive-type connected to an electrode wire having a constant electric potential, as its source, and has a gate electrode connected to the electrode wire. A lateral bipolar transistor includes a third diffusion layer of a reverse conductive-type formed with a constant spaced distance with respect to the second diffusion layer and connected to the metal terminal, as its collector, and also has the second diffusion layer as its emitter, and furthermore has the one conductive-type region as its base. Thus, a semiconductor device is protected from an electrostatic discharge (ESD) breakdown device even though having high density and a high operating speed.

摘要翻译： 半导体器件包括设置在半导体衬底上的金属端子和保护元件。 保护元件包括绝缘栅场效应晶体管。 晶体管具有形成在半导体衬底的一个导电类型区域上并以金属端子连接的反向导电型的第一扩散层作为其源极。 晶体管还包括连接到具有恒定电位的电极线作为其源极的反向导电型的第二扩散层，并且具有连接到电极线的栅电极。 横向双极晶体管包括反向导电型的第三扩散层，该第三扩散层相对于第二扩散层具有恒定的间隔距离并且连接到作为其集电极的金属端子，并且还具有第二扩散层作为其发射极， 并且还具有一个导电型区域作为其基底。 因此，即使具有高密度和高操作速度，半导体器件也被保护免受静电放电（ESD）击穿器件的影响。

公开(公告)号：US5521413A

公开(公告)日：1996-05-28

申请号：US346307

申请日：1994-11-23

申请人： Kaoru Narita

发明人： Kaoru Narita

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L23/485 ,  H01L27/06 ,  H01L29/74 ,  H01L23/62 ,  H02H3/20

CPC分类号： H01L23/485 ,  H01L2924/0002

摘要： On the surface of a p-type semiconductor substrate, an n-type diffusion layer is formed. The diffusion layer is in contact with an aluminum wiring via a contact hole formed through an interlayer insulation layer to electrical connection. Immediately beneath the contact portion of the aluminum wiring, a contact n-type diffusion layer having higher impurity concentration than the n-type diffusion layer and having deeper junction depth. Outside of the contact n-type diffusion layer is surrounded by a low impurity concentration n well. With the construction, when an electrostatic pulse is applied to an external terminal connected to the shallow diffusion layer, junction breakdown of the diffusion layer can be successfully prevented.

摘要翻译： 在p型半导体衬底的表面上形成n型扩散层。 扩散层通过形成在层间绝缘层上的接触孔与铝布线接触以进行电连接。 在铝布线的接触部分的正下方，具有比n型扩散层更高的杂质浓度并且具有更深的结深度的接触n型扩散层。 在接触n型扩散层外面被低杂质浓度n阱包围。 利用这种结构，当静电脉冲施加到连接到浅扩散层的外部端子时，可以成功地防止扩散层的结击穿。

公开(公告)号：US5436487A

公开(公告)日：1995-07-25

申请号：US248729

申请日：1994-05-25

申请人： Kaoru Narita

发明人： Kaoru Narita

IPC分类号： H01L21/822 ,  G11C11/409 ,  H01L21/8234 ,  H01L27/04 ,  H01L27/06 ,  H01L27/088 ,  H01L29/78 ,  H03K5/02 ,  H03K17/16 ,  H03K17/687 ,  H03K19/003 ,  H03K19/094 ,  H01L27/02 ,  H01L29/72

CPC分类号： H03K19/09403 ,  H03K19/00315 ,  H03K19/00361

摘要： In an output circuit having first and second MOS transistors in series between a first power supply line and a second power supply line, and a third MOS transistor, the gates of the first and second transistors are connected to first and second input nodes, respectively, and an output node is provided between the first and second MOS transistors. The third MOS transistor is connected between one of the input nodes and the output node. The gate of the third MOS transistor is connected to a third power supply line.

摘要翻译： 在具有串联在第一电源线和第二电源线之间的第一和第二MOS晶体管和第三MOS晶体管的输出电路中，第一和第二晶体管的栅极分别连接到第一和第二输入节点， 并且在第一和第二MOS晶体管之间提供输出节点。 第三MOS晶体管连接在输入节点之一和输出节点之间。 第三MOS晶体管的栅极连接到第三电源线。

公开(公告)号：US07868257B2

公开(公告)日：2011-01-11

申请号：US10598134

申请日：2005-03-09

申请人： Taras Kushta ,  Kaoru Narita ,  Hirokazu Tohya ,  Takanori Saeki ,  Tomoyuki Kaneko

发明人： Taras Kushta ,  Kaoru Narita ,  Hirokazu Tohya ,  Takanori Saeki ,  Tomoyuki Kaneko

IPC分类号： H01R12/04 ,  H05K1/11

CPC分类号： H05K1/0222 ,  H05K1/0269 ,  H05K3/429 ,  H05K2201/09536 ,  H05K2201/09618 ,  H05K2201/09718 ,  H05K2201/09809

摘要： A via transmission line for a multilayer printed circuit board (PCB) in which a wave guiding channel is formed by a signal via or a number of signal vias, an assembly of ground vias surrounding the signal via or corresponding number of coupled signal vias, a set of ground plates from conductor layers of the multilayer PCB, and a clearance hole. In this via transmission line, the signal via, or the number of signal vias forms an inner conductive boundary, ground vias and ground plates from conductor layers of the multilayer PCB form an outer conductive boundary, and the clearance hole provides both isolation of the inner conductive boundary from the outer conductive boundary and high-performance broadband operation of the via transmission line by means of the predetermined clearance hole cross-sectional shape and dimensions where the cross-sectional shape of the clearance hole is defined by the arrangement of ground vias in the outer conductive boundary and dimensions of the clearance hole are determined according to a method to minimize frequency-dependent return losses caused by specific corrugations of the outer conductive boundary formed by ground plates in the wave guiding channel of the via transmission line.

摘要翻译： 一种用于多层印刷电路板（PCB）的通孔传输线，其中通过信号通道或多个信号通路形成波导通道，围绕信号通孔或相应数量的耦合信号通孔的接地通孔的组件， 多层PCB的导体层的接地板组以及间隙孔。 在这个通过传输线路中，信号通孔或信号通道的数量形成内部导电边界，从多层PCB的导体层形成的接地孔和接地板形成外部导电边界，并且间隙孔提供内部 通过外部导电边界的导电边界和通孔传输线的高性能宽带操作，借助于预定的间隙孔横截面形状和尺寸，其中间隙孔的横截面形状由接地通孔的布置 根据通过在通孔传输线的波导通道中由接地板形成的外导电边界的特定波纹引起的频率相关的返回损耗的方法来确定间隙孔的外导电边界和尺寸。

公开(公告)号：US07463122B2

公开(公告)日：2008-12-09

申请号：US10558888

申请日：2004-06-01

申请人： Taras Kushta ,  Kaoru Narita ,  Takanori Saeki ,  Tomoyuki Kaneko ,  Hirokazu Tohya

发明人： Taras Kushta ,  Kaoru Narita ,  Takanori Saeki ,  Tomoyuki Kaneko ,  Hirokazu Tohya

IPC分类号： H01P1/04

CPC分类号： H05K1/0222 ,  H01P3/06 ,  H05K1/024 ,  H05K1/0251 ,  H05K3/429 ,  H05K2201/0187 ,  H05K2201/09063 ,  H05K2201/09536 ,  H05K2201/09618 ,  H05K2201/09718 ,  H05K2201/09809

摘要： A compact via transmission line for a printed circuit board having preferred characteristic impedance and capable of miniaturizing the printed circuit board including a multilayer printed circuit board, and extending the frequency range of a via transmission line mounted on the printed circuit board, and a design method of the same. The transmission line has a central conductor forming an inner conductor layer boundary make up a signal via hole, a plurality of via holes arranged around the central conductor form an outer conductor layer boundary, and a plurality of conductor plates formed of a printed circuit board conductor layer, is further provided with a constitutive parameter adjustment clearance hole between the inner and outer conductor layer boundaries of the compact via transmission line, and electrically isolates to prevent cross-talk of a signal propagating through a signal via hole with other signals in a high-frequency signal band.

摘要翻译： 一种用于具有优选特性阻抗并能够使包括多层印刷电路板的印刷电路板小型化并且扩展安装在印刷电路板上的通孔传输线的频率范围的印刷电路板的紧凑型通路传输线，以及设计方法 一样的。 传输线具有形成内导体层边界的中心导体，构成信号通孔，围绕中心导体布置的多个通孔形成外导体层边界，以及由印刷电路板导体形成的多个导体板 通过传输线在压缩体的内部和外部导体层边界之间进一步设置本构参数调整间隙孔，并且电隔离以防止通过信号通孔传播的信号与其他信号在高电平中的串扰 频率信号频带。

公开(公告)号：US06191633B1

公开(公告)日：2001-02-20

申请号：US09149115

申请日：1998-09-09

申请人： Takeo Fujii ,  Kaoru Narita ,  Yoko Horiguchi

发明人： Takeo Fujii ,  Kaoru Narita ,  Yoko Horiguchi

IPC分类号： H03K508

CPC分类号： H03K5/08 ,  H01L27/0251 ,  H01L27/0255 ,  H01L27/0288 ,  H01L2924/0002 ,  H01L2924/00

摘要： A Semiconductor integrated circuit with a protection circuit against electrostatic discharge. A clamping element is connected with MIS transistor to prevent the breakdown under the charged device model. A parasitic bipolar transistor, a MOS transistor or MIS transistor whose gate is composed of an insulating film thicker than that of the transfer gate, can be used as the clamping element.

摘要翻译： 一个具有防静电放电保护电路的半导体集成电路。 夹紧元件与MIS晶体管连接，以防止充电器件型号下的击穿。 可以使用寄生双极晶体管，MOS晶体管或MIS晶体管，其栅极由比传输栅极厚的绝缘膜构成，可用作夹紧元件。

公开(公告)号：US5869871A

公开(公告)日：1999-02-09

申请号：US896952

申请日：1997-07-18

申请人： Kaoru Narita

发明人： Kaoru Narita

IPC分类号： H01L21/822 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/04 ,  H01L27/088 ,  H01L29/78 ,  H01L23/62

CPC分类号： H01L27/0251

摘要： In a semiconductor device including a semiconductor substrate, first and second external terminals, a first impurity diffusion region connected to the first external terminal, and second and third impurity diffusion regions forming a MIS transistor, one of the second and third impurity diffusion regions facing the first impurity region is connected to the second external terminal. The distance between the first diffusion region and the MIS transistor is substantially smaller than a certain value compared to conventional device.

摘要翻译： 在包括半导体衬底，第一和第二外部端子的半导体器件中，连接到第一外部端子的第一杂质扩散区域和形成MIS晶体管的第二和第三杂质扩散区域，第二和第三杂质扩散区域中的一个面向 第一杂质区连接到第二外部端子。 与常规器件相比，第一扩散区域和MIS晶体管之间的距离明显小于一定值。

公开(公告)号：US5724219A

公开(公告)日：1998-03-03

申请号：US655188

申请日：1996-05-30

申请人： Kaoru Narita

发明人： Kaoru Narita

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L23/60 ,  H01L27/02 ,  H01L27/06 ,  H02H3/22

CPC分类号： H01L27/0251

摘要： A semiconductor device according to this invention comprises a first power supply (Vcc) wiring, a second power supply (Gnd) wiring, a first, a second and a third protective elements (3-1, 3-2 and 3-3), a first connecting wiring which connects in common one ends of the first, the second and the third protective elements, a second connecting wiring which connects the other ends of the first, the second and the third protective elements, and a third connecting wiring which connects the first connecting wiring and the first power supply wiring. The third connecting wiring has a resistance which is higher than that of the first connecting wiring.

摘要翻译： 根据本发明的半导体器件包括第一电源（Vcc）布线，第二电源（Gnd）布线，第一，第二和第三保护元件（3-1,3-2和3-3）， 连接在第一，第二和第三保护元件的共同一端的第一连接布线，连接第一，第二和第三保护元件的另一端的第二连接布线，以及连接第 第一连接线和第一电源线。 第三连接布线具有高于第一连接布线的电阻。

公开(公告)号：US5717559A

公开(公告)日：1998-02-10

申请号：US686545

申请日：1996-07-26

申请人： Kaoru Narita

发明人： Kaoru Narita

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/60 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H02H9/00

CPC分类号： H01L27/0262 ,  H01L27/0255 ,  H01L27/0288 ,  H01L29/87

摘要： An input/output protection device for protecting an internal circuit of an integrated circuit formed on a P-type substrate, from an electrostatic discharge (ESD), includes a thyristor connected between a terminal connected to the internal circuit and a common wiring conductor. The protection device comprises a N-well formed in the P-type substrate, a first P-type diffused region formed in the N-well and connected to the terminal, a first N-diffused region formed to adjoin the first N-well, a second P-type diffused region formed in close proximity to the first N-type diffused region, and a second N-type diffused region formed in the P-type substrate and connected to the common wiring conductor. An external resistor is connected between the first P-type diffused region and the first N-type diffused region, and another external resistor is connected between the second P-type diffused region and the second N-type diffused region. A diode is constituted of the first N-diffused region and the second P-type diffused region in close proximity to each other, so that the diode has a low parasitic resistance. Thus, when a negative electrostatic pulse is applied to the terminal, the diode allows a forward current to flow from the common wiring conductor to the terminal through a low impedance path including the first resistor, the diode and the second resistor.

摘要翻译： 用于保护形成在P型衬底上的集成电路的内部电路与静电放电（ESD）的输入/输出保护装置包括连接在连接到内部电路的端子和公共布线导体之间的晶闸管。 保护装置包括在P型衬底中形成的N阱，形成在N阱中并连接到端子的第一P型扩散区域，形成为邻接第一N阱的第一N扩散区域， 形成在第一N型扩散区域附近的第二P型扩散区域和形成在P型衬底中并连接到公共布线导体的第二N型扩散区域。 在第一P型扩散区域和第一N型扩散区域之间连接有外部电阻器，在第二P型扩散区域和第二N型扩散区域之间连接有另一个外部电阻器。 二极管由彼此靠近的第一N扩散区域和第二P型扩散区域构成，使得二极管具有低寄生电阻。 因此，当向端子施加负静电脉冲时，二极管允许正向电流通过包括第一电阻器，二极管和第二电阻器的低阻抗路径从公共布线导体流到端子。