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41.发明授权Etch stop layer of reduced thickness for patterning a dielectric material in a contact level of closely spaced transistors 有权用于图案化紧密间隔晶体管的接触电平的介电材料的减小厚度的蚀刻停止层公开(公告)号：US08097542B2
公开(公告)日：2012-01-17
申请号：US12260147
申请日：2008-10-29
IPC分类号： H01L21/31
CPC分类号： H01L21/76826 , H01L21/76832 , H01L21/823412 , H01L21/823425 , H01L21/823807 , H01L29/7843 , Y02P80/30
摘要： In a dual stress liner approach, an intermediate etch stop material may be provided on the basis of a plasma-assisted oxidation process rather than by deposition so the corresponding thickness of the etch stop material may be reduced. Consequently, the resulting aspect ratio may be less pronounced compared to conventional strategies, thereby reducing deposition-related irregularities which may translate into a significant reduction of yield loss, in particular for highly scaled semiconductor devices.
摘要翻译： 在双重应力衬垫方法中，可以基于等离子体辅助氧化工艺而不是通过沉积来提供中间蚀刻停止材料，从而减小蚀刻停止材料的对应厚度。 因此，与常规策略相比，所产生的纵横比可能不太明显，从而减少沉积相关的不规则性，这可能转化为产量损失的显着降低，特别是对于高度缩放的半导体器件。
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公开(公告)号：US20100025776A1
公开(公告)日：2010-02-04
申请号：US12472969
申请日：2009-05-27
IPC分类号： H01L27/088 , H01L21/28
CPC分类号： H01L21/823462 , H01L21/28035 , H01L21/823456 , H01L27/11 , H01L29/4238 , H01L29/513
摘要： In a memory cell, the drive current capabilities of the transistors may be adjusted by locally providing an increased gate dielectric thickness and/or gate length of one or more of the transistors of the memory cell. That is, the gate length and/or the gate dielectric thickness may vary along the transistor width direction, thereby providing an efficient mechanism for adjusting the effective drive current capability while at the same time allowing the usage of a simplified geometry of the active region, which may result in enhanced production yield due to enhanced process uniformity. In particular, the probability of creating short circuits caused by nickel silicide portions may be reduced.
摘要翻译： 在存储器单元中，晶体管的驱动电流能力可以通过局部地提供存储单元的一个或多个晶体管的增加的栅介质厚度和/或栅极长度来调节。 也就是说，栅极长度和/或栅极电介质厚度可以沿晶体管宽度方向变化，从而提供用于调节有效驱动电流能力的有效机构，同时允许使用有源区域的简化几何形状， 这可能由于增加的工艺均匀性而导致产量提高。 特别地，可能减少由硅化镍部分引起的产生短路的可能性。
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43.发明申请METHOD FOR REDUCING DEFECTS OF GATE OF CMOS DEVICES DURING CLEANING PROCESSES BY MODIFYING A PARASITIC PN JUNCTION 有权通过修改PARASITIC PN JUNCTION来减少清洁过程中CMOS器件的栅极缺陷的方法公开(公告)号：US20090273036A1
公开(公告)日：2009-11-05
申请号：US12397574
申请日：2009-03-04
IPC分类号： H01L27/092 , H01L21/4763
CPC分类号： H01L21/823842 , H01L21/823871
摘要： By incorporating nitrogen into the P-doped regions and N-doped regions of the gate electrode material prior to patterning the gate electrode structure, yield losses due to reactive wet chemical cleaning processes may be significantly reduced.
摘要翻译： 通过在对栅电极结构进行构图之前将氮掺入P掺杂区域和栅极电极材料的N掺杂区域中，可以显着降低由于反应性湿化学清洗过程引起的屈服损失。
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44.发明申请METHOD OF FORMING A SEMICONDUCTOR STRUCTURE COMPRISING TRANSISTOR ELEMENTS WITH DIFFERENTLY STRESSED CHANNEL REGIONS 审中-公开形成包含不同应力通道区域的晶体管元件的半导体结构的方法公开(公告)号：US20070207583A1
公开(公告)日：2007-09-06
申请号：US11745671
申请日：2007-05-08
IPC分类号： H01L21/8236
CPC分类号： H01L29/7842 , H01L21/823412 , H01L21/823437 , H01L21/823807 , H01L21/823828 , H01L29/7843
摘要： A semiconductor structure comprising a first transistor element and a second transistor element is provided. Stress in channel regions of the first and the second transistor element is controlled by forming stressed layers having a predetermined stress over the transistors. The stressed layers may be used as etch stop layers in the formation of contact vias through an interlayer dielectric formed over the transistors.
摘要翻译： 提供包括第一晶体管元件和第二晶体管元件的半导体结构。 通过在晶体管上形成具有预定应力的应力层来控制第一和第二晶体管元件的沟道区域中的应力。 应力层可以用作通过在晶体管上形成的层间电介质形成接触孔的蚀刻停止层。
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45.发明授权Semiconductor device having T-shaped gate structure comprising in situ sidewall spacers and method of forming the semiconductor device 失效具有包括原位侧壁间隔件的T形门结构的半导体器件和形成半导体器件的方法公开(公告)号：US07148145B2
公开(公告)日：2006-12-12
申请号：US10400598
申请日：2003-03-27
IPC分类号： H01L21/302
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/28114
摘要： Polysilicon lines are formed, featuring an upper portion extending beyond the lower portion that defines the required CD. Accordingly, metal silicide layers of increased dimensions can be formed on the upper portion of the polysilicon lines so that the resulting gate structures exhibit a very low final sheet resistance. Moreover, in situ sidewall spacers are realized during the process for forming the polysilicon lines and without additional steps and/or costs.
摘要翻译： 形成多晶硅线，具有延伸超过限定所需CD的下部的上部。 因此，可以在多晶硅线路的上部形成尺寸增加的金属硅化物层，使得所得到的栅极结构表现出非常低的最终薄层电阻。 此外，在形成多晶硅生产线的过程中实现原位侧壁间隔物，并且没有额外的步骤和/或成本。
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46.发明授权Method of removing features using an improved removal process in the fabrication of a semiconductor device 失效使用改进的去除工艺在半导体器件的制造中去除特征的方法公开(公告)号：US07041583B2
公开(公告)日：2006-05-09
申请号：US10624776
申请日：2003-07-22
IPC分类号： H01L21/3205 , H01L21/336
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/28052 , H01L29/665 , H01L29/7833
摘要： A method for improving the etch behavior of disposable features in the fabrication of a semiconductor device is disclosed. The semiconductor device comprises a bottom anti-reflective coating layer and/or a disposable sidewall spacer which are to be removed in a subsequent etch removal process. The bottom anti-reflective coating layer and/or the disposable sidewall spacer are irradiated by heavy inert ions to alter the structure of the irradiated features and to increase concurrently the etch rate of the employed materials, for example, silicon nitride or silicon reacted nitride.
摘要翻译： 公开了一种在制造半导体器件中改善一次性特征的蚀刻行为的方法。 半导体器件包括底部抗反射涂层和/或一次性侧壁间隔物，其将在随后的蚀刻去除过程中被去除。 底部抗反射涂层和/或一次性侧壁间隔物被重的惰性离子照射以改变被照射特征的结构，并同时增加所用材料的蚀刻速率，例如氮化硅或硅反应的氮化物。
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47.发明申请Technique for evaluating local electrical characteristics in semiconductor devices 审中-公开评估半导体器件局部电气特性的技术公开(公告)号：US20060022197A1
公开(公告)日：2006-02-02
申请号：US11099755
申请日：2005-04-06
IPC分类号： H01L23/58
CPC分类号： G01R31/2884 , H01L22/32 , H01L2924/0002 , H01L2924/00
摘要： By providing a test structure including a plurality of test pads, the anisotropic behavior of stress and strain influenced electrical characteristics, such as the electron mobility, may be determined in a highly efficient manner. Moreover, the test pads may enable the detection of stress and strain induced modifications with a spatial resolution in the order of magnitude of individual circuit elements.
摘要翻译： 通过提供包括多个测试焊盘的测试结构，可以以高效的方式确定应力和应变影响的电特性（例如电子迁移率）的各向异性行为。 此外，测试焊盘可以使得能够以单个电路元件的数量级的空间分辨率来检测应力和应变诱发的修改。
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48.发明申请公开(公告)号：US20050151202A1
公开(公告)日：2005-07-14
申请号：US11072142
申请日：2005-03-04
IPC分类号： H01L21/20 , H01L21/265 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/10 , H01L29/78 , H01L29/76
CPC分类号： H01L21/823807 , H01L29/1033 , H01L29/105 , H01L29/1054 , H01L29/6659
摘要： An epitaxially grown channel layer is provided on a well structure after ion implantation steps and heat treatment steps are performed to establish a required dopant profile in the well structure. The channel layer may be undoped or slightly doped, as required, so that the finally obtained dopant concentration in the channel layer is significantly reduced compared to a conventional device to thereby provide a retrograde dopant profile in a channel region of a field effect transistor. Additionally, a barrier diffusion layer may be provided between the well structure and the channel layer to reduce up-diffusion during any heat treatments carried out after the formation of the channel layer. The final dopant profile in the channel region may be adjusted by the thickness of the channel layer, the thickness and the composition of the diffusion barrier layer and any additional implantation steps to introduce dopant atoms in the channel layer.
摘要翻译： 在离子注入步骤之后在阱结构上提供外延生长的沟道层，并且进行热处理步骤以在阱结构中建立所需的掺杂剂分布。 根据需要，沟道层可以是未掺杂的或稍微掺杂的，使得与常规器件相比，沟道层中最终获得的掺杂剂浓度显着降低，从而在场效应晶体管的沟道区域中提供逆向掺杂物分布。 此外，可以在阱结构和沟道层之间提供阻挡扩散层，以在形成沟道层之后进行的任何热处理期间减小向上扩散。 可以通过沟道层的厚度，扩散阻挡层的厚度和组成以及在沟道层中引入掺杂剂原子的任何额外的注入步骤来调整沟道区中的最终掺杂物分布。
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49.发明申请SOI field effect transistor element having a recombination region and method of forming same 审中-公开具有复合区域的SOI场效应晶体管元件及其形成方法公开(公告)号：US20050037548A1
公开(公告)日：2005-02-17
申请号：US10949089
申请日：2004-09-24
IPC分类号： H01L21/336 , H01L29/786 , H01L21/00
CPC分类号： H01L29/78696 , H01L29/66772 , H01L29/78612 , H01L29/78684
摘要： An SOI transistor element and a method of fabricating the same is disclosed, wherein a high concentration of stationary point defects is created by including a region within the active transistor area that has a slight lattice mismatch. In one particular embodiment, a silicon germanium layer is provided in the active area having a high concentration of point defects due to relaxing the strain of the silicon germanium layer upon heat treating the transistor element. Due to the point defects, the recombination rate is significantly increased, thereby reducing the number of charged carriers stored in the active area.
摘要翻译： 公开了SOI晶体管元件及其制造方法，其中通过在有源晶体管区域内包含具有轻微晶格失配的区域来产生高浓度的固定点缺陷。 在一个特定实施例中，由于在对晶体管元件进行热处理时放松硅锗层的应变，在有源区域中提供了具有高浓度点缺陷的硅锗层。 由于点缺陷，复合率显着增加，从而减少存储在有源区域中的带电载流子数量。
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公开(公告)号：US06593197B2
公开(公告)日：2003-07-15
申请号：US09811733
申请日：2001-03-19
IPC分类号： H01L21336
CPC分类号： H01L29/6659
摘要： This invention provides methods of forming a field-effect transistor in an integrated circuit using self-aligning technology on the basis of a sidewall spacer masking procedure, both for defining the device isolation features and the source and drain regions. The active region is defined after patterning the gate electrode by means of deposition and etch processes instead of overlay alignment technique. Thus, the present invention enables an increase of the integration density of semiconductor devices, a minimization of the parasitic capacitances in field-effect transistor devices, and a quicker manufacturing process.
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