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    Semiconductor device for reducing leak currents and controlling a threshold voltage and using a thin channel structure
    42.
    发明授权
    Semiconductor device for reducing leak currents and controlling a threshold voltage and using a thin channel structure 失效
    用于减少泄漏电流并控制阈值电压并使用薄沟道结构的半导体器件

    公开(公告)号：US06576943B1

    公开(公告)日：2003-06-10

    申请号：US09512827

    申请日：2000-02-25

    申请人： Tomoyuki Ishii ,  Kazuo Yano ,  Toshiyuki Mine

    发明人： Tomoyuki Ishii ,  Kazuo Yano ,  Toshiyuki Mine

    IPC分类号： H01L27108

    CPC分类号： G11C16/0433 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10873 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/78642

    摘要： A very thin semiconductor film is used for channels of semiconductor memory elements such that leak currents are reduced by the quantum-mechanical containment effect in the direction of film thickness. The amount of electrical charge accumulated in each charge accumulating region is used to change the conductance between a source region and a drain region of each read transistor structure. This conductance change is utilized for data storage. The thickness of the channel of the write transistor structure is preferably no more than 5 nm. According to one embodiment, the channel of the write transistor is formed by a semiconductor film deposited on a surface intersecting a principal plane of the substrate.

    摘要翻译： 非常薄的半导体膜用于半导体存储元件的通道，使得漏电流通过膜厚度方向的量子力学容纳效应而降低。 使用在每个电荷累积区域中累积的电荷量来改变每个读取的晶体管结构的源极区域和漏极区域之间的电导。 该电导变化用于数据存储。 写入晶体管结构的沟道的厚度优选不大于5nm。 根据一个实施例，写入晶体管的沟道由沉积在与衬底的主平面相交的表面上的半导体膜形成。

    Semiconductor integrated circuit device
    43.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US06356118B1

    公开(公告)日：2002-03-12

    申请号：US09549711

    申请日：2000-04-14

    申请人： Kunihito Rikino ,  Yasuhiko Sasaki ,  Kazuo Yano ,  Naoki Kato

    发明人： Kunihito Rikino ,  Yasuhiko Sasaki ,  Kazuo Yano ,  Naoki Kato

    IPC分类号： H03K19094

    CPC分类号： H01L27/092 ,  H01L27/0203 ,  H03K19/1737

    摘要： A pass-transistor logic circuit configuration that can form a high-speed chip in a small area with short wire length. In a selector circuit PMOS and NMOS transistors with different gate signals but with the same drain outputs are arranged, respectively, so their diffusion layers are shared. The PMOS and NMOS are staggered so that their gates are almost in line. With this arrangement, wires connecting drains of the PMOS and NMOS and wires connecting sources of the PMOS and NMOS do not intersect each other, so they can be wired with only the first wiring layer. Further, gate input signals can be wired with only polysilicon wires without crossing each other. The pass-transistor logic circuit is made to pass through the signal buffers before or after it is connected to the selector. This can make a compact, fast circuit.

    摘要翻译： 通过晶体管逻辑电路配置，可以在短的线长度的小区域内形成高速芯片。 在选择器电路中，分别布置具有不同栅极信号但具有相同漏极输出的PMOS和NMOS晶体管，因此它们的扩散层被共享。 PMOS和NMOS交错，使得它们的栅极几乎成一行。 通过这种布置，连接PMOS和NMOS的漏极的电线和连接PMOS和NMOS的源极的线彼此不相交，因此它们可以仅与第一布线层布线。 此外，栅极输入信号可以仅连接多晶硅线，而不会彼此交叉。 通过晶体管逻辑电路在连接到选择器之前或之后通过信号缓冲器。 这可以使紧凑，快速的电路。

    Logic circuit including combined pass transistor and CMOS circuit and a method of synthesizing the logic circuit
    44.
    发明授权
    Logic circuit including combined pass transistor and CMOS circuit and a method of synthesizing the logic circuit 有权
    包括组合传输晶体管和CMOS电路的逻辑电路和合成逻辑电路的方法

    公开(公告)号：US06313666B1

    公开(公告)日：2001-11-06

    申请号：US09331780

    申请日：1999-06-24

    申请人： Shunzo Yamashita ,  Kazuo Yano

    发明人： Shunzo Yamashita ,  Kazuo Yano

    IPC分类号： H03K19094

    CPC分类号： H03K19/1736 ,  G06F17/505 ,  H03K19/1737

    摘要： In order to produce a logic circuit excellent in circuit characteristics which are area, delay time and power consumption by combining pass transistor logic circuits and CMOS logic circuits, a binary decision diagram is created from a Boolean function, and respective nodes of the diagram are mapped into 2-inut, 1-output, 1-control input pass transistor selectors to synthesize a pass transistor logic circuit. In the pass transistor logic circuit, a pass transistor selector operating as a NAND or NOR logic with any one of its two inputs excluding the control input being fixed to a logical constant “1” or “0” is replaced with a CMOS gate operating as a NAND or NOR logic logically equivalent to the pass tansistor selector if the value of a predetermined circuit characteristic obtained by the replacement is closer to an optimal value (if the resulting logic circuit is smaller in area, delay time or power consumption than the original pass transistor logic circuit).

    摘要翻译： 为了通过组合传输晶体管逻辑电路和CMOS逻辑电路来产生电路特性优异的逻辑电路，其面积，延迟时间和功率消耗，从布尔函数创建二进制决策图，并将该图的各个节点映射 成为2-inut，1输出，1控制输入通道晶体管选择器，以合成传输晶体管逻辑电路。 在传输晶体管逻辑电路中，作为NAND或NOR逻辑的传输晶体管选择器，其两个输入中的任何一个不包括固定在逻辑常数“1”或“0”的控制输入，被替换为CMOS门 如果通过替换获得的预定电路特性的值更接近于最佳值（如果所得到的逻辑电路的面积，延迟时间或功耗比原始通路小，则逻辑上等效于通过转换器选择器的NAND或NOR逻辑） 晶体管逻辑电路）。

    Semiconductor integrated circuit comprised of pass-transistor circuits with different mutual connections
    46.
    发明授权
    Semiconductor integrated circuit comprised of pass-transistor circuits with different mutual connections 失效
    半导体集成电路由具有不同相互连接的通过晶体管电路组成

    公开(公告)号：US5923189A

    公开(公告)日：1999-07-13

    申请号：US633053

    申请日：1996-04-16

    申请人： Yasuhiko Sasaki ,  Kazuo Yano ,  Shunzo Yamashita ,  Koichi Seki

    发明人： Yasuhiko Sasaki ,  Kazuo Yano ,  Shunzo Yamashita ,  Koichi Seki

    IPC分类号： G06F17/50 ,  H03K19/173 ,  H03K19/0948

    CPC分类号： H03K19/1736 ,  G06F17/505 ,  H03K19/1737

    摘要： For the relation between the first and second pass-transistor circuits (PT1, PT2), the output signal of the preceding-stage is supplied to the gate of the succeeding-stage, and for the relation between the second and third pass-transistor circuits (PT2, PT3), the output signal of the preceding-stage is supplied to the source-drain path of the succeeding-stage. The first pass-transistor circuit (PT1) receives on its first input node (In1) and second input node (In2) the first input signal and the second input signal that are logically independent from each other. This logic circuit requires a smaller number of transistors and is capable of reducing the power consumption and delay and accomplishing an intricate logic function.

    摘要翻译： 对于第一和第二通过晶体管电路（PT1，PT2）之间的关系，前级的输出信号被提供给后级的栅极，并且对于第二和第三通过晶体管电路之间的关系 （PT2，PT3），将前级的输出信号提供给后级的源极 - 漏极路径。 第一通过晶体管电路（PT1）在第一输入节点（In1）和第二输入节点（In2）上接收逻辑上彼此独立的第一输入信号和第二输入信号。 该逻辑电路需要较少数量的晶体管，并且能够降低功耗并延迟并完成复杂的逻辑功能。

    Semiconductor integrated logic circuit device using a pass transistor
    47.
    发明授权
    Semiconductor integrated logic circuit device using a pass transistor 失效

    公开(公告)号：US5872716A

    公开(公告)日：1999-02-16

    申请号：US703189

    申请日：1996-08-26

    申请人： Kazuo Yano ,  Yasuhiko Sasaki

    发明人： Kazuo Yano ,  Yasuhiko Sasaki

    IPC分类号： H01L21/82 ,  H01L27/02 ,  H01L27/118 ,  H03K19/173 ,  G06F13/00

    CPC分类号： H03K19/1735 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2924/14

    摘要： The semiconductor integrated circuit enjoys a high performance and can be produced at a low production cost and within a short time. A cell has an internal circuit connection such that an output terminal is connected to a plurality of input terminals through source-drain paths of active devices connected in the tree form, and gate electrodes of the active devices are connected to other input terminals. Two such cells having the same internal circuit connection, the same disposition of the internal circuit devices and the same disposition of the input/output terminals are disposed on the same chip, and mutually different logics can be accomplished by changing the form of application of input signals from outside the cells to the input terminals. A chip area of an integrated circuit designed by CAD using a cell library can be reduced and a high speed circuit operation can be attained. The present invention provides remarkable effect for improving performance of an ASIC, a microprocessor, etc., and for reducing the cost of production.

    Logic circuit and data processing apparatus using the same
    49.
    发明授权
    Logic circuit and data processing apparatus using the same 失效
    逻辑电路及使用其的数据处理装置

    公开(公告)号：US5148387A

    公开(公告)日：1992-09-15

    申请号：US480674

    申请日：1990-02-15

    申请人： Kazuo Yano ,  Koichiro Ishibashi ,  Tetsuya Nakagawa ,  Katsuhiro Shimohigashi ,  Osamu Minato

    发明人： Kazuo Yano ,  Koichiro Ishibashi ,  Tetsuya Nakagawa ,  Katsuhiro Shimohigashi ,  Osamu Minato

    IPC分类号： G06F7/50 ,  G06F7/501

    CPC分类号： G06F7/5016

    摘要： A logic circuit includes first, second, third, fourth, fifth and sixth field effect transistors or FETs, input nodes and an output node. The fifth and sixth FETs are connected to the output node. The first and third FETs are connected to the fifth FET. The second and fourth FETs are connected to the sixth FET. The first and second FETs are connected to the first input node. The third and fourth FETs are connected to the second node. A first signal is supplied to the first input node. A second signal is supplied to gate electrodes of the first and fourth FETs. A signal having a phase opposite to the second signal is supplied to gate electrodes of the second and third FETs. A third signal is supplied to the second input node. One signal selected from the first, second and the third signals is supplied to the gate electrode of the fifth FET. A signal having a phase opposite to the signal supplied to the gate electrode of the fifth FET is supplied to the gate electrode of the sixth FET. An output signal related to the first, second and third input signals is generated from the output node. The output signal is, for example, a carry output signal or alternatively a majority decision logic output signal.

    摘要翻译： 逻辑电路包括第一，第二，第三，第四，第五和第六场效应晶​​体管或FET，输入节点和输出节点。 第五和第六FET连接到输出节点。 第一和第三FET连接到第五FET。 第二和第四FET连接到第六FET。 第一和第二FET连接到第一输入节点。 第三和第四FET连接到第二节点。 第一信号被提供给第一输入节点。 向第一和第四FET的栅电极提供第二信号。 具有与第二信号相反的相位的信号被提供给第二和第三FET的栅电极。 第三信号被提供给第二输入节点。 从第一，第二和第三信号中选择的一个信号被提供给第五FET的栅电极。 具有与提供给第五FET的栅电极的信号相反的相位的信号被提供给第六FET的栅电极。 从输出节点生成与第一，第二和第三输入信号有关的输出信号。 输出信号例如是进位输出信号或多数决定逻辑输出信号。

    Semiconductor device
    50.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US4864382A

    公开(公告)日：1989-09-05

    申请号：US148052

    申请日：1988-01-25

    申请人： Masaaki Aoki ,  Kazuo Yano ,  Toshiaki Masuhara

    发明人： Masaaki Aoki ,  Kazuo Yano ,  Toshiaki Masuhara

    IPC分类号： H01L27/108 ,  H01L29/10 ,  H01L29/167 ,  H01L29/66

    CPC分类号： H01L29/66992 ,  H01L27/10805 ,  H01L29/1083 ,  H01L29/167 ,  Y10S257/919

    摘要： A MOS memory is formed in a semiconductor bulk, whereas a barrier semiconductor layer is disposed at the boundary between a MOS memory portion and the semiconductor bulk in order to reduce the effect of undesirable carriers excited by .alpha.-particles. The barrier semiconductor layer is designed to permit operation of the memory at low temperature while reducing the incidence of soft errors due to .alpha.-particles.

    摘要翻译： 在半导体本体中形成MOS存储器，而在MOS存储器部分和半导体体之间的边界处设置阻挡半导体层，以便降低由α-粒子激发的不希望的载流子的影响。 阻挡半导体层被设计为允许在低温下操作存储器，同时减少由于α-粒子引起的软错误的发生。