公开(公告)号：US08389988B2

公开(公告)日：2013-03-05

申请号：US12571554

申请日：2009-10-01

申请人： Shunpei Yamazaki ,  Kengo Akimoto ,  Shigeki Komori ,  Hideki Uochi ,  Tomoya Futamura ,  Takahiro Kasahara

发明人： Shunpei Yamazaki ,  Kengo Akimoto ,  Shigeki Komori ,  Hideki Uochi ,  Tomoya Futamura ,  Takahiro Kasahara

IPC分类号： H01L28/72

CPC分类号： G02F1/136204 ,  H01L27/0248 ,  H01L27/1225 ,  H01L27/124 ,  H01L33/0041 ,  H01L2924/0002 ,  H01L2924/00

摘要： In order to take advantage of the properties of a display device including an oxide semiconductor, a protective circuit and the like having appropriate structures and a small occupied area are necessary. The protective circuit is formed using a non-linear element which includes a gate insulating film covering a gate electrode; a first oxide semiconductor layer over the gate insulating film; a channel protective layer covering a region which overlaps with a channel formation region of the first oxide semiconductor layer; and a first wiring layer and a second wiring layer each of which is formed by stacking a conductive layer and a second oxide semiconductor layer and over the first oxide semiconductor layer. The gate electrode is connected to a scan line or a signal line, the first wiring layer or the second wiring layer is directly connected to the gate electrode.

公开(公告)号：US08373443B2

公开(公告)日：2013-02-12

申请号：US13116372

申请日：2011-05-26

申请人： Jun Koyama ,  Kengo Akimoto ,  Masashi Tsubuku

发明人： Jun Koyama ,  Kengo Akimoto ,  Masashi Tsubuku

IPC分类号： H03K19/20 ,  H03K19/094

CPC分类号： H03K19/094 ,  H01L27/0883 ,  H01L27/1225 ,  H03K19/09407 ,  H03K19/09421 ,  H03K19/096

摘要： An object is to apply a transistor using an oxide semiconductor to a logic circuit including an enhancement transistor. The logic circuit includes a depletion transistor 101 and an enhancement transistor 102. The transistors 101 and 102 each include a gate electrode, a gate insulating layer, a first oxide semiconductor layer, a second oxide semiconductor layer, a source electrode, and a drain electrode. The transistor 102 includes a reduction prevention layer provided over a region in the first oxide semiconductor layer between the source electrode and the drain electrode.

公开(公告)号：US08343817B2

公开(公告)日：2013-01-01

申请号：US12535713

申请日：2009-08-05

申请人： Hidekazu Miyairi ,  Kengo Akimoto ,  Yasuo Nakamura

发明人： Hidekazu Miyairi ,  Kengo Akimoto ,  Yasuo Nakamura

IPC分类号： H01L21/00

CPC分类号： H01L29/78696 ,  H01L21/02323 ,  H01L21/02565 ,  H01L21/32139 ,  H01L21/465 ,  H01L21/467 ,  H01L21/4763 ,  H01L21/47635 ,  H01L27/1225 ,  H01L29/0692 ,  H01L29/1033 ,  H01L29/24 ,  H01L29/263 ,  H01L29/42364 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/495 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/78633 ,  H01L29/7869 ,  H01L29/78693

摘要： To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is manufactured with a small number of steps. After a channel protective layer is formed over an oxide semiconductor film containing In, Ga, and Zn, a film having n-type conductivity and a conductive film are formed, and a resist mask is formed over the conductive film. The conductive film, the film having n-type conductivity, and the oxide semiconductor film containing In, Ga, and Zn are etched using the channel protective layer and gate insulating films as etching stoppers with the resist mask, so that source and drain electrode layers, a buffer layer, and a semiconductor layer are formed.

公开(公告)号：US08329506B2

公开(公告)日：2012-12-11

申请号：US12618944

申请日：2009-11-16

申请人： Kengo Akimoto ,  Junichiro Sakata ,  Takuya Hirohashi ,  Masahiro Takahashi ,  Hideyuki Kishida ,  Akiharu Miyanaga

发明人： Kengo Akimoto ,  Junichiro Sakata ,  Takuya Hirohashi ,  Masahiro Takahashi ,  Hideyuki Kishida ,  Akiharu Miyanaga

IPC分类号： H01L21/00

CPC分类号： H01L29/7869 ,  H01L21/02565 ,  H01L21/28079 ,  H01L21/28158 ,  H01L29/04 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78693

摘要： It is an object to provide an oxide semiconductor which is suitable for use in a semiconductor device. Alternatively, it is another object to provide a semiconductor device using the oxide semiconductor. Provided is a semiconductor device including an In—Ga—Zn—O based oxide semiconductor layer in a channel formation region of a transistor. In the semiconductor device, the In—Ga—Zn—O based oxide semiconductor layer has a structure in which crystal grains represented by InGaO3(ZnO)m (m=1) are included in an amorphous structure represented by InGaO3(ZnO)m (m>0).

摘要翻译： 本发明的目的是提供一种适用于半导体器件的氧化物半导体。 或者，另一目的是提供一种使用氧化物半导体的半导体器件。 提供了在晶体管的沟道形成区域中包括In-Ga-Zn-O系氧化物半导体层的半导体器件。 在半导体器件中，In-Ga-Zn-O系氧化物半导体层具有以InGaO 3（ZnO）m（m = 1）表示的晶粒包含在由InGaO 3（ZnO）m（ m> 0）。

公开(公告)号：US08318551B2

公开(公告)日：2012-11-27

申请号：US12627204

申请日：2009-11-30

申请人： Kengo Akimoto ,  Toshinari Sasaki

发明人： Kengo Akimoto ,  Toshinari Sasaki

IPC分类号： H01L21/84 ,  H01L29/10 ,  H01L29/12

CPC分类号： H01L29/7869 ,  H01L27/1225 ,  H01L29/41733 ,  H01L29/66969

摘要： A gate electrode layer over a substrate; a gate insulating layer over the gate electrode layer; a first source electrode layer and a first drain electrode layer over the gate insulating layer; an oxide semiconductor layer over the gate insulating layer; and a second source electrode layer and a second drain electrode layer over the oxide semiconductor layer. A first part, a second part, and a third part of a bottom surface are in contact with the first source electrode layer, the first drain electrode layer, and the gate insulating layer respectively. A first part and a second part of the top surface are in contact with the second source electrode layer and the second drain electrode layer respectively. The first source electrode layer and the first drain electrode layer are electrically connected to the second source electrode layer and the second drain electrode layer respectively.

摘要翻译： 衬底上的栅电极层; 栅电极层上的栅极绝缘层; 栅极绝缘层上的第一源极电极层和第一漏极电极层; 栅极绝缘层上的氧化物半导体层; 以及在所述氧化物半导体层上的第二源极电极层和第二漏极电极层。 第一部分，第二部分和底部表面的第三部分分别与第一源极电极层，第一漏极电极层和栅极绝缘层接触。 上表面的第一部分和第二部分分别与第二源极电极层和第二漏极电极层接触。 第一源极电极层和第一漏极电极层分别与第二源极电极层和第二漏极电极层电连接。

公开(公告)号：US08288199B2

公开(公告)日：2012-10-16

申请号：US12184401

申请日：2008-08-01

申请人： Kengo Akimoto ,  Tatsuya Honda ,  Norihito Sone

发明人： Kengo Akimoto ,  Tatsuya Honda ,  Norihito Sone

IPC分类号： H01L21/00

摘要： An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

公开(公告)号：US08274077B2

公开(公告)日：2012-09-25

申请号：US12184443

申请日：2008-08-01

申请人： Kengo Akimoto ,  Tatsuya Honda ,  Norihito Sone

发明人： Kengo Akimoto ,  Tatsuya Honda ,  Norihito Sone

IPC分类号： H01L29/10

CPC分类号： H01L29/78696 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02266 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/428 ,  H01L21/465 ,  H01L21/477 ,  H01L27/1225 ,  H01L27/1285 ,  H01L29/04 ,  H01L29/045 ,  H01L29/7869

摘要： An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

摘要翻译： 本发明的目的是提供一种半导体器件，其制造工艺不复杂并且可以通过以氧化锌为代表的氧化物半导体膜形成薄膜晶体管来制造成本。 对于半导体器件，在基板上形成栅电极; 形成覆盖栅电极的栅极绝缘膜; 在栅绝缘膜上形成氧化物半导体膜; 并且在氧化物半导体膜上形成第一导电膜和第二导电膜。 氧化物半导体膜在沟道区域中至少具有结晶化区域。

公开(公告)号：US08158975B2

公开(公告)日：2012-04-17

申请号：US12575564

申请日：2009-10-08

申请人： Kengo Akimoto

发明人： Kengo Akimoto

IPC分类号： H01L29/10 ,  H01L29/12 ,  H01L21/00 ,  H01L21/16

CPC分类号： H01L29/7869 ,  H01L27/1225 ,  H01L29/45 ,  H01L29/78606

摘要： Electric characteristics and reliability of a thin film transistor are impaired by diffusion of an impurity element into a channel region. The present invention provides a thin film transistor in which aluminum atoms are unlikely to be diffused to an oxide semiconductor layer. A thin film transistor including an oxide semiconductor layer including indium, gallium, and zinc includes source or drain electrode layers in which first conductive layers including aluminum as a main component and second conductive layers including a high-melting-point metal material are stacked. An oxide semiconductor layer 113 is in contact with the second conductive layers and barrier layers including aluminum oxide as a main component, whereby diffusion of aluminum atoms to the oxide semiconductor layer is suppressed.

公开(公告)号：US08158464B2

公开(公告)日：2012-04-17

申请号：US12411957

申请日：2009-03-26

申请人： Kengo Akimoto

发明人： Kengo Akimoto

IPC分类号： H01L29/04

CPC分类号： H01L29/7869 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/78621

摘要： To provide a semiconductor device in which a defect or fault is not generated and a manufacturing method thereof even if a ZnO semiconductor film is used and a ZnO film to which an n-type or p-type impurity is added is used for a source electrode and a drain electrode. The semiconductor device includes a gate insulating film formed by using a silicon oxide film or a silicon oxynitride film over a gate electrode, an Al film or an Al alloy film over the gate insulating film, a ZnO film to which an n-type or p-type impurity is added over the Al film or the Al alloy film, and a ZnO semiconductor film over the ZnO film to which an n-type or p-type impurity is added and the gate insulating film.

摘要翻译： 为了提供其中不产生缺陷或故障的半导体器件及其制造方法，即使使用ZnO半导体膜，并且将添加有n型或p型杂质的ZnO膜用于源电极 和漏电极。 半导体器件包括通过栅极绝缘膜上的栅电极，Al膜或Al合金膜上的氧化硅膜或氮氧化硅膜形成的栅极绝缘膜，n型或p型的ZnO膜 在Al膜或Al合金膜上添加型杂质，在添加有n型或p型杂质的ZnO膜上的ZnO半导体膜和栅极绝缘膜。

公开(公告)号：US08129719B2

公开(公告)日：2012-03-06

申请号：US12549415

申请日：2009-08-28

申请人： Shunpei Yamazaki ,  Kengo Akimoto

发明人： Shunpei Yamazaki ,  Kengo Akimoto

IPC分类号： H01L29/12 ,  H01L21/34 ,  H01L29/786

CPC分类号： H01L29/78696 ,  H01L21/02318 ,  H01L21/02323 ,  H01L21/0234 ,  H01L21/02565 ,  H01L29/247 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693

摘要： An object is to provide favorable interface characteristics of a thin film transistor including an oxide semiconductor layer without mixing of an impurity such as moisture. Another object is to provide a semiconductor device including a thin film transistor having excellent electric characteristics and high reliability, and a method by which a semiconductor device can be manufactured with high productivity. A main point is to perform oxygen radical treatment on a surface of a gate insulating layer. Accordingly, there is a peak of the oxygen concentration at an interface between the gate insulating layer and a semiconductor layer, and the oxygen concentration of the gate insulating layer has a concentration gradient. The oxygen concentration is increased toward the interface between the gate insulating layer and the semiconductor layer.

摘要翻译： 本发明的目的是提供一种薄膜晶体管的有利的界面特性，该薄膜晶体管包括氧化物半导体层，而不混入杂质如水分。 另一个目的是提供一种包括具有优异的电特性和高可靠性的薄膜晶体管的半导体器件，以及可以以高生产率制造半导体器件的方法。 要点是在栅极绝缘层的表面进行氧自由基处理。 因此，在栅极绝缘层与半导体层之间的界面处存在氧浓度的峰值，并且栅极绝缘层的氧浓度具有浓度梯度。 氧浓度朝向栅极绝缘层和半导体层之间的界面增加。