公开(公告)号：US08045411B2

公开(公告)日：2011-10-25

申请号：US11785059

申请日：2007-04-13

申请人： Kyung-Hoon Kim ,  Patrick B. Moran

发明人： Kyung-Hoon Kim ,  Patrick B. Moran

IPC分类号： G11C7/04

CPC分类号： G11C7/04 ,  G11C11/406 ,  G11C11/40626 ,  G11C2029/5002 ,  G11C2211/4067

摘要： A semiconductor memory device capable of measuring a temperature without the influence of noise includes a temperature sensing device for sensing a current temperature in response to a control signal, wherein the semiconductor memory device enters a power save mode for a predetermined time starting from an activation of the control signal and wherein the power save mode has substantially no power consumption. A method for driving a semiconductor memory device in accordance with the present invention includes sensing a current temperature in response to a control signal and entering a power save mode for a predetermined time starting from an activation of the control signal, wherein the power save mode has substantially no power consumption.

摘要翻译： 能够在不受噪声影响的情况下测量温度的半导体存储器件包括用于响应于控制信号感测当前温度的温度感测装置，其中半导体存储器件从激活时开始预定的时间进入省电模式 所述控制信号并且其中所述省电模式基本上没有功率消耗。 根据本发明的用于驱动半导体存储器件的方法包括响应于控制信号感测当前温度并且从控制信号的激活开始预定时间进入省电模式，其中省电模式具有 基本上没有功耗。

公开(公告)号：US07961026B2

公开(公告)日：2011-06-14

申请号：US12003676

申请日：2007-12-31

申请人： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon

发明人： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon

IPC分类号： H03H11/26

CPC分类号： H03L7/0995 ,  H03K3/0322 ,  H03K5/133 ,  H03K2005/00208 ,  H03K2005/00234 ,  H03L2207/06

摘要： A phase locked loop that generates an internal clock by controlling a delay time of a delay cell according to conditions of PVT, thereby improving a jitter characteristic of the internal clock. The delay cell includes a first current controller for controlling first and second currents in response to a control voltage, and a second current controller for controlling the first and second currents in response to frequency range selection signals. The phase locked loop includes a phase comparator for comparing a reference clock with a feedback clock, a control voltage generator for generating a control voltage corresponding to an output of the phase comparator, and a voltage controlled oscillator for generating an internal clock having a frequency in response to the control voltage and one or more frequency range control signals, wherein the feedback clock is generated using the internal clock.

摘要翻译： 通过根据PVT的条件控制延迟单元的延迟时间来产生内部时钟的锁相环，从而提高内部时钟的抖动特性。 延迟单元包括响应于控制电压控制第一和第二电流的第一电流控制器，以及响应频率范围选择信号控制第一和第二电流的第二电流控制器。 锁相环包括用于将参考时钟与反馈时钟进行比较的相位比较器，用于产生对应于相位比较器的输出的控制电压的控制电压发生器和用于产生具有频率的内部时钟的压控振荡器 响应于控制电压和一个或多个频率范围控制信号，其中使用内部时钟产生反馈时钟。

公开(公告)号：US07884647B2

公开(公告)日：2011-02-08

申请号：US12326990

申请日：2008-12-03

申请人： Kyung-Hoon Kim ,  Dae-Han Kwon ,  Taek-Sang Song

发明人： Kyung-Hoon Kim ,  Dae-Han Kwon ,  Taek-Sang Song

IPC分类号： H03K19/0175

CPC分类号： H03K19/018528

摘要： There is provided an output driver, which includes a pre-driver configured to generate a main driving control signal in response to a data signal, a main driver configured to drive an output terminal in response to the main driving control signal, an auxiliary driving control signal generator configured to generate an auxiliary driving control signal having an activation interval corresponding to the data signal and an interval control signal, and an auxiliary driver configured to drive the output terminal in response to the auxiliary driving control signal.

摘要翻译： 提供了一种输出驱动器，其包括配置为响应于数据信号产生主驱动控制信号的预驱动器，配置成响应于主驱动控制信号驱动输出端的主驱动器，辅助驱动控制 信号发生器，其被配置为产生具有与数据信号和间隔控制信号对应的激活间隔的辅助驱动控制信号，以及配置为响应于辅助驱动控制信号来驱动输出端子的辅助驱动器。

公开(公告)号：US07816962B2

公开(公告)日：2010-10-19

申请号：US12284060

申请日：2008-09-18

申请人： Kyung-Hoon Kim

发明人： Kyung-Hoon Kim

IPC分类号： H03L7/06

CPC分类号： G11C7/222 ,  G11C7/22 ,  H03L7/0814 ,  H03L7/085

摘要： A delay locked loop can remove a jitter component that inevitably occurs due to feedback latency in the conventional DLL. That is, the present invention has benefit of removing the jitter component by controlling the delay lines based on the predicted data. The delay locked loop includes a pattern detecting unit for generating and storing a noise pattern by detecting inputted noise data, a pre-delay control unit for determining a delay amount depending on the output of the pattern detecting unit, and a pre-delay line for delaying an internal clock depending on the delay amount that is determined by the pre-delay control means.

摘要翻译： 延迟锁定环可以消除由于常规DLL中的反馈等待时间而不可避免地发生的抖动分量。 也就是说，本发明通过基于预测数据控制延迟线来消除抖动分量的益处。 延迟锁定环包括：图案检测单元，用于通过检测输入的噪声数据产生和存储噪声模式;预延迟控制单元，用于根据模式检测单元的输出确定延迟量;以及预延迟线， 根据由预延迟控制装置确定的延迟量来延迟内部时钟。

公开(公告)号：US07668028B2

公开(公告)日：2010-02-23

申请号：US11819812

申请日：2007-06-29

申请人： Kyung-Hoon Kim ,  Yong-Ki Kim

发明人： Kyung-Hoon Kim ,  Yong-Ki Kim

IPC分类号： G11C7/00 ,  G11C7/10 ,  G11C8/00

CPC分类号： G11C29/48 ,  G11C5/04 ,  G11C29/1201 ,  G11C2029/5602

摘要： A dual in-line memory module (DIMM) for use in test includes a memory array with a plurality of memories, a test signal input/output unit, and a normal data input/output unit. The test signal input/output unit is provided in the respective memories to perform an input/output operation of a test signal with an external test mode controller for a test mode operation. The normal data input/output unit is provided in the respective memories to perform an input/output operation of a normal data with an external memory controller for a normal mode operation.

摘要翻译： 用于测试的双列直插存储器模块（DIMM）包括具有多个存储器的存储器阵列，测试信号输入/输出单元和正常数据输入/输出单元。 测试信号输入/输出单元设置在各个存储器中，以便通过用于测试模式操作的外部测试模式控制器执行测试信号的输入/输出操作。 正常数据输入/输出单元设置在相应的存储器中，以用于正常模式操作的外部存储器控制器执行正常数据的输入/输出操作。

公开(公告)号：US20090273493A1

公开(公告)日：2009-11-05

申请号：US12215772

申请日：2008-06-30

申请人： Kyung-Hoon Kim ,  Dae-Han Kwon ,  Chang-Kyu Choi ,  Taek-Sang Song

发明人： Kyung-Hoon Kim ,  Dae-Han Kwon ,  Chang-Kyu Choi ,  Taek-Sang Song

IPC分类号： H03M9/00

CPC分类号： H03M9/00

摘要： A parallel-to-serial converter includes a data input unit configured to receive a plurality of parallel data by using a plurality of clock signals having different phases, and a parallel-to-serial conversion unit configured to sequentially select and output an output signal of the data input unit by using a plurality of clock signals having a predetermined phase difference from the plurality of clock signals used in the data input unit.

摘要翻译： 并行转换器包括：数据输入单元，被配置为通过使用具有不同相位的多个时钟信号来接收多个并行数据;以及并行到串行转换单元，被配置为顺序地选择和输出 数据输入单元通过使用与数据输入单元中使用的多个时钟信号具有预定相位差的多个时钟信号。

公开(公告)号：US20090273385A1

公开(公告)日：2009-11-05

申请号：US12347446

申请日：2008-12-31

申请人： Chang-Kyu CHOI ,  Kyung-Hoon Kim

发明人： Chang-Kyu CHOI ,  Kyung-Hoon Kim

IPC分类号： H03L5/00

CPC分类号： H03K5/08 ,  H04L25/0264 ,  H04L25/028

摘要： An output circuit of a semiconductor device includes a signal selector configured to receive first and second input data signals and sequentially outputting the first and second input data signals in response to a phase signal; and an output level controller configured to control a voltage level of an output signal of the signal selector based on the first and second input data signals.

摘要翻译： 半导体器件的输出电路包括：信号选择器，被配置为接收第一和第二输入数据信号，并响应于相位信号顺序地输出第一和第二输入数据信号; 以及输出电平控制器，被配置为基于第一和第二输入数据信号来控制信号选择器的输出信号的电压电平。

公开(公告)号：US07612593B2

公开(公告)日：2009-11-03

申请号：US12005923

申请日：2007-12-28

申请人： Kyung-Hoon Kim ,  Jun-Woo Lee ,  Dae-Kun Yoon ,  Taek-Sang Song

发明人： Kyung-Hoon Kim ,  Jun-Woo Lee ,  Dae-Kun Yoon ,  Taek-Sang Song

IPC分类号： H03K5/02

CPC分类号： H03K5/1534 ,  G11C7/22 ,  G11C7/222 ,  H03K5/1565

摘要： Semiconductor memory device with duty correction circuit includes a clock edge detector configured to generate first and second detection pulses in response to a transition timing of a common clock signal in an initial measurement operation; a duty detector configured to compare the first and second detection pulses to output comparison result signals; and a code counter configured to control the duty detector based on the comparison signals outputted from the duty detector in the initial measurement operation.

摘要翻译： 具有占空比校正电路的半导体存储器件包括：时钟边缘检测器，被配置为响应于在初始测量操作中的公共时钟信号的转变定时产生第一和第二检测脉冲; 负载检测器，被配置为将所述第一和第二检测脉冲与输出比较结果信号进行比较; 以及代码计数器，被配置为基于在初始测量操作中从占空比检测器输出的比较信号来控制占空比检测器。

公开(公告)号：US07551501B2

公开(公告)日：2009-06-23

申请号：US11647409

申请日：2006-12-29

申请人： Kyung-Hoon Kim ,  Patrick B. Moran

发明人： Kyung-Hoon Kim ,  Patrick B. Moran

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G01K13/00 ,  G11C5/143 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/20 ,  G11C11/406 ,  G11C11/40626 ,  G11C2029/5002 ,  G11C2211/4061

摘要： A semiconductor memory device includes a thermosensor that senses present temperatures of the device and confirms whether the temperature values are valid. The thermosensor includes a temperature sensing unit, a storage unit and an initializing unit. The temperature sensing unit senses temperatures in response to a driving signal. The storage unit stores output signals of the temperature sensing unit and outputs temperature values. The initializing unit initializes the storage unit after a predetermined time from an activation of the driving signal. A driving method includes driving the thermosensor in response to the driving signal, requesting a re-driving after a predetermined time from the activation of the driving signal, and re-driving the thermosensor in response to the driving signal input again.

摘要翻译： 半导体存储器件包括感测器件的当前温度并确认温度值是否有效的热敏传感器。 热敏传感器包括温度检测单元，存储单元和初始化单元。 温度感测单元响应于驱动信号感测温度。 存储单元存储温度感测单元的输出信号并输出​​温度值。 初始化单元在从驱动信号的激活开始的预定时间之后初始化存储单元。 驱动方法包括响应于驱动信号驱动热敏传感器，在从驱动信号的激活开始的预定时间之后请求重新驱动，并且响应于再次输入驱动信号重新驱动热敏传感器。

公开(公告)号：US07541831B2

公开(公告)日：2009-06-02

申请号：US11987937

申请日：2007-12-06

申请人： Kyung-Hoon Kim

发明人： Kyung-Hoon Kim

IPC分类号： H03K17/16

CPC分类号： H04L25/0278 ,  G01R31/31715 ,  G11C29/02 ,  G11C29/022 ,  G11C29/50008 ,  G11C2207/2254

摘要： A semiconductor memory device includes a reference signal generating unit for generating a reference signal; a comparing unit for comparing the reference signal with a test signal applied to a test pad to output an adjusted value after adjusting the adjusted value until the test signal is equal to the reference signal; an impedance measuring unit for measuring an impedance of the test pad based on the adjusted value to output the test signal; an impedance adjusting unit for adjusting an impedance of a data I/O pad to have an impedance value corresponding to the adjusted value outputted when the test signal is equal to the reference signal; an impedance control unit for controlling the comparing unit so that the adjusted value is outputted when the test signal is equal to the reference signal; and a reference signal control unit for adjusting a voltage level of the reference signal.

摘要翻译： 半导体存储器件包括用于产生参考信号的参考信号产生单元; 比较单元，用于将参考信号与施加到测试垫的测试信号进行比较，以在调整了调整值直到测试信号等于参考信号之后输出调整值; 阻抗测量单元，用于基于所述调整值来测量所述测试垫的阻抗以输出所述测试信号; 阻抗调整单元，用于调整数据I / O焊盘的阻抗，使阻抗值对应于当测试信号等于参考信号时输出的调整值; 阻抗控制单元，用于控制比较单元，使得当测试信号等于参考信号时，输出调整值; 以及用于调整参考信号的电压电平的参考信号控制单元。