公开(公告)号：US07285480B1

公开(公告)日：2007-10-23

申请号：US11279063

申请日：2006-04-07

申请人： Rajiv V. Joshi ,  Louis C. Hsu ,  Oleg Gluschenkov

发明人： Rajiv V. Joshi ,  Louis C. Hsu ,  Oleg Gluschenkov

IPC分类号： H01L21/00

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/78654

摘要： An Integrated Circuit (IC) chip that may be a bulk CMOS IC chip with silicon on insulator (SOI) Field Effect Transistors (FETs) and method of making the chip. The IC chip includes areas with pockets of buried insulator strata and FETs formed on the strata are SOI FETs. The SOI FETs may include Partially Depleted SOI (PD-SOI) FETs and Fully Depleted SOI (FD-SOI) FETs and the chip may include bulk FETs as well. The FETs are formed by contouring the surface of a wafer, conformally implanting oxygen to a uniform depth, and planarizing to remove the Buried OXide (BOX) in bulk FET regions.

摘要翻译： 一种集成电路（IC）芯片，其可以是具有绝缘体上硅（SOI）场效应晶体管（FET）和制造芯片的方法的体CMOS IC芯片。 IC芯片包括具有埋入绝缘体层的凹坑的区域，并且在层上形成的FET是SOI FET。 SOI FET可以包括部分耗尽的SOI（PD-SOI）FET和完全耗尽的SOI（FD-SOI）FET，并且芯片也可以包括体FET。 FET通过轮廓化晶片的表面，将氧气保形地均匀地注入到均匀的深度，并平坦化以去除体FET区域中的掩埋氧化物（BOX）来形成。

公开(公告)号：US06864540B1

公开(公告)日：2005-03-08

申请号：US10851530

申请日：2004-05-21

申请人： Rama Divakaruni ,  Louis C. Hsu ,  Rajiv V. Joshi ,  Carl J. Radens

发明人： Rama Divakaruni ,  Louis C. Hsu ,  Rajiv V. Joshi ,  Carl J. Radens

IPC分类号： H01L21/336 ,  H01L29/45 ,  H01L29/76 ,  H01L29/786

CPC分类号： H01L29/66553 ,  H01L29/458 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7842 ,  H01L29/78618 ,  H01L29/78684

摘要： The invention includes a field effect transistor (FET) on an insulator layer, and integrated circuit (IC) on SOI chip including the FETs and a method of forming the IC. The FETs include a thin channel with raised source/drain (RSD) regions at each end on an insulator layer, e.g., on an ultra-thin silicon on insulator (SOI) chip. Isolation trenches at each end of the FETs, i.e., at the end of the RSD regions, isolate and define FET islands. Insulating sidewalls at each RSD region sandwich the FET gate between the RSD regions. The gate dielectric may be a high K dielectric. Salicide on the RSD regions and, optionally, on the gates reduce device resistances.

摘要翻译： 本发明包括在绝缘体层上的场效应晶体管（FET）和包括FET的SOI芯片上的集成电路（IC）以及形成IC的方法。 FET包括在绝缘体层上的每个端部（例如，在绝缘体上的超薄绝缘体（SOI））芯片上的源极/漏极（RSD）区域上升的薄沟道。 在FET的每个端部，即在RSD区域的末端处的隔离沟槽隔离并限定FET岛。 每个RSD区域的绝缘侧壁将RSD区域之间的FET栅极夹在中间。 栅极电介质可以是高K电介质。 RSD区域上和可选地在栅极上的杀菌剂降低了器件电阻。

公开(公告)号：US09058887B2

公开(公告)日：2015-06-16

申请号：US11928258

申请日：2007-10-30

申请人： Louis C. Hsu ,  Conal E. Murray ,  Chandrasekhar Narayan ,  Chih-Chao Yang

发明人： Louis C. Hsu ,  Conal E. Murray ,  Chandrasekhar Narayan ,  Chih-Chao Yang

IPC分类号： G06F17/50 ,  G11C17/18 ,  H04L12/701 ,  H04L29/08

CPC分类号： G11C17/18 ,  G06F17/5045 ,  H04L29/08072 ,  H04L45/00

摘要： The present invention provides a reprogrammable electrically blowable fuse and associated design structure. The electrically blowable fuse is programmed using an electro-migration effect and is reprogrammed using a reverse electro-migration effect. The state (i.e., “opened” or “closed”) of the electrically blowable fuse is determined by a sensing system which compares a resistance of the electrically blowable fuse to a reference resistance.

摘要翻译： 本发明提供了一种可再编程的电可熔熔丝和相关的设计结构。 电可熔熔丝使用电迁移效应进行编程，并使用反向电迁移效应重新编程。 可电熔熔丝的状态（即“打开”或“关闭”）由将电可电熔丝的电阻与参考电阻进行比较的感测系统确定。

公开(公告)号：US08759175B2

公开(公告)日：2014-06-24

申请号：US13429556

申请日：2012-03-26

申请人： Louis C. Hsu ,  Xu Ouyang ,  Ping-Chuan Wang ,  Zhijian J. Yang

发明人： Louis C. Hsu ,  Xu Ouyang ,  Ping-Chuan Wang ,  Zhijian J. Yang

IPC分类号： H01L21/00

CPC分类号： H01L21/28273 ,  H01L27/11521 ,  H01L29/7881

摘要： A flash memory structure having an enhanced capacitive coupling coefficient ratio (CCCR) may be fabricated in a self-aligned manner while using a semiconductor substrate that has an active region that is recessed within an aperture with respect to an isolation region that surrounds the active region. The flash memory structure includes a floating gate that does not rise above the isolation region, and that preferably consists of a single layer that has a U shape. The U shape facilitates the enhanced capacitive coupling coefficient ratio.

摘要翻译： 具有增强的电容耦合系数比（CCCR）的闪速存储器结构可以以自对准方式制造，同时使用半导体衬底，该半导体衬底具有相对于围绕有源区域的隔离区域在孔内凹入的有源区域 。 闪速存储器结构包括不在隔离区上方升起的浮栅，并且优选地由具有U形的单层组成。 U形增强了电容耦合系数比。

公开(公告)号：US08598641B2

公开(公告)日：2013-12-03

申请号：US13287170

申请日：2011-11-02

申请人： Howard H. Chen ,  Louis C. Hsu ,  Jack A. Mandelman ,  Chun-Yung Sung

发明人： Howard H. Chen ,  Louis C. Hsu ,  Jack A. Mandelman ,  Chun-Yung Sung

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L21/823437 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  Y10S977/734 ,  Y10S977/742 ,  Y10S977/749 ,  Y10S977/815 ,  Y10S977/955

摘要： A semiconductor device and a method of fabricating a semiconductor device, wherein the method includes forming, on a substrate, a plurality of planarized fin bodies to be used for customized fin field effect transistor (FinFET) device formation; forming a nitride spacer around each of the plurality of fin bodies; forming an isolation region in between each of the fin bodies; and coating the plurality of fin bodies, the nitride spacers, and the isolation regions with a protective film. The fabricated semiconductor device is adapted to be used in customized applications as a customized semiconductor device.

摘要翻译： 一种半导体器件和半导体器件的制造方法，其中该方法包括在衬底上形成多个用于定制鳍状场效应晶体管（FinFET）器件形成的平坦化翅片体; 在所述多个翅片体中的每一个周围形成氮化物间隔物; 在每个翅片体之间形成隔离区域; 并用保护膜涂覆多个翅片体，氮化物间隔物和隔离区域。 制造的半导体器件适用于定制应用中作为定制的半导体器件。

公开(公告)号：US08339893B2

公开(公告)日：2012-12-25

申请号：US12566862

申请日：2009-09-25

申请人： Yuen H. Chan ,  Louis C. Hsu ,  Xu Ouyang ,  Robert C. Wong

发明人： Yuen H. Chan ,  Louis C. Hsu ,  Xu Ouyang ,  Robert C. Wong

IPC分类号： G11C8/00

CPC分类号： G11C8/16 ,  G11C11/412

摘要： A static random access memory (SRAM) cell includes a first read port, the first read port having a first beta ratio; and a write port, the write port having a second beta ratio that is substantially lower than the first beta ratio. A static random access memory (SRAM) array includes a plurality of SRAM cells, an SRAM cell including a first read port, the first read port having a first beta ratio; and a write port, the write port having a second beta ratio that is substantially lower than the first beta ratio.

摘要翻译： 静态随机存取存储器（SRAM）单元包括第一读取端口，第一读取端口具有第一β比率; 和写入端口，所述写入端口具有基本上低于所述第一β比率的第二β比率。 静态随机存取存储器（SRAM）阵列包括多个SRAM单元，包括第一读取端口的SRAM单元，第一读取端口具有第一β比率; 和写入端口，所述写入端口具有基本上低于所述第一β比率的第二β比率。

公开(公告)号：US20120184076A1

公开(公告)日：2012-07-19

申请号：US13429556

申请日：2012-03-26

申请人： Louis C. Hsu ,  Xu Ouyang ,  Ping-Chuan Wang ,  Zhijian J. Yang

发明人： Louis C. Hsu ,  Xu Ouyang ,  Ping-Chuan Wang ,  Zhijian J. Yang

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  H01L27/11521 ,  H01L29/7881

摘要： A flash memory structure having an enhanced capacitive coupling coefficient ratio (CCCR) may be fabricated in a self-aligned manner while using a semiconductor substrate that has an active region that is recessed within an aperture with respect to an isolation region that surrounds the active region. The flash memory structure includes a floating gate that does not rise above the isolation region, and that preferably consists of a single layer that has a U shape. The U shape facilitates the enhanced capacitive coupling coefficient ratio.

摘要翻译： 具有增强的电容耦合系数比（CCCR）的闪速存储器结构可以以自对准方式制造，同时使用半导体衬底，该半导体衬底具有相对于围绕有源区域的隔离区域在孔内凹入的有源区域 。 闪速存储器结构包括不在隔离区上方升起的浮栅，并且优选地由具有U形的单层组成。 U形有助于增强电容耦合系数比。

公开(公告)号：US08138085B2

公开(公告)日：2012-03-20

申请号：US13093798

申请日：2011-04-25

申请人： Howard H. Chen ,  Louis C. Hsu ,  Lawrence S. Mok ,  J. Campbell Scott

发明人： Howard H. Chen ,  Louis C. Hsu ,  Lawrence S. Mok ,  J. Campbell Scott

IPC分类号： H01L21/44

CPC分类号： H01L21/324 ,  H01L21/268 ,  H01L24/01 ,  H01L25/0657 ,  H01L27/0688 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/14 ,  H01L2924/00

摘要： A laser annealing method for annealing a stacked semiconductor structure having at least two stacked layers is disclosed. A laser beam is focused on a lower layer of the stacked layers. The laser beam is then scanned to anneal features in the lower layer. The laser beam is then focused on an upper layer of the stacked layers, and the laser beam is scanned to anneal features in the upper layer. The laser has a wavelength of less than one micrometer. The beam size, depth of focus, energy dosage, and scan speed of the laser beam are programmable. Features in the lower layer are offset from features in the upper layer such that these features do not overlap along a plane parallel to a path of the laser beam. Each of the stacked layers includes active devices, such as transistors. Also, the first and second layers may be annealed simultaneously.

摘要翻译： 公开了一种用于退火具有至少两个堆叠层的层叠半导体结构的激光退火方法。 激光束聚焦在堆叠层的下层。 然后扫描激光束以退火下层中的特征。 然后将激光束聚焦在堆叠层的上层上，并且激光束被扫描以退火上层中的特征。 激光器的波长小于1微米。 激光束的光束尺寸，焦深，能量投射和扫描速度是可编程的。 较低层中的特征偏离上层中的特征，使得这些特征不沿着与激光束的路径平行的平面重叠。 堆叠层中的每一个包括诸如晶体管的有源器件。 此外，第一层和第二层可以同时退火。

公开(公告)号：US20120043597A1

公开(公告)日：2012-02-23

申请号：US13287170

申请日：2011-11-02

申请人： Howard H. Chen ,  Louis C. Hsu ,  Jack A. Mandelman ,  Chun-Yung Sung

发明人： Howard H. Chen ,  Louis C. Hsu ,  Jack A. Mandelman ,  Chun-Yung Sung

IPC分类号： H01L29/772

CPC分类号： H01L21/823437 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  Y10S977/734 ,  Y10S977/742 ,  Y10S977/749 ,  Y10S977/815 ,  Y10S977/955

摘要： A semiconductor device and a method of fabricating a semiconductor device, wherein the method comprises forming, on a substrate, a plurality of planarized fin bodies to be used for customized fin field effect transistor (FinFET) device formation; forming a nitride spacer around each of the plurality of fin bodies; forming an isolation region in between each of the fin bodies; and coating the plurality of fin bodies, the nitride spacers, and the isolation regions with a protective film. The fabricated semiconductor device is used in customized applications as a customized semiconductor device.

摘要翻译： 一种半导体器件和半导体器件的制造方法，其中所述方法包括在衬底上形成多个用于定制鳍状场效应晶体管（FinFET）器件形成的平坦化翅片体; 在所述多个翅片体中的每一个周围形成氮化物间隔物; 在每个翅片体之间形成隔离区域; 并用保护膜涂覆多个翅片体，氮化物间隔物和隔离区域。 制造的半导体器件用作定制应用中的定制半导体器件。

公开(公告)号：US07727888B2

公开(公告)日：2010-06-01

申请号：US11216198

申请日：2005-08-31

申请人： Chih-Chao Yang ,  Louis C. Hsu ,  Rajiv V. Joshi

发明人： Chih-Chao Yang ,  Louis C. Hsu ,  Rajiv V. Joshi

IPC分类号： H01L29/41 ,  H01L21/44

CPC分类号： H01L21/76814 ,  H01L21/76805 ,  H01L21/76808 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76855 ,  Y10S438/964

摘要： An interconnect structure and a method for forming the same are described. Specifically, under the present invention, a gouge is created within a via formed in the interconnect structure before any trenches are formed. This prevents the above-mentioned trench damage from occurring. That is, the bottom surface of the trenches will have a roughness of less than approximately 20 nm, and preferably less than approximately 10 nm. In addition to the via, gouge and trench(es), the interconnect structure of the present invention includes at least two levels of metal wiring. Further, in a typical embodiment, the interconnect structure utilizes any dielectrics having a dielectric constant no greater than approximately 5.0.

摘要翻译： 描述了互连结构及其形成方法。 具体地说，在本发明中，在形成任何沟槽之前，在互连结构中形成的通孔内形成一个沟槽。 这防止了上述的沟槽损坏发生。 也就是说，沟槽的底表面将具有小于约20nm，优选小于约10nm的粗糙度。 除了通孔，沟槽和沟槽之外，本发明的互连结构还包括至少两层金属布线。 此外，在典型的实施例中，互连结构利用介电常数不大于约5.0的任何电介质。