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128 条记录 (耗时 0.034 秒)

    Fast BICMOS active-pixel sensor cell with fast NPN emitter-follower readout
    41.
    发明授权
    Fast BICMOS active-pixel sensor cell with fast NPN emitter-follower readout 失效
    快速的BICMOS有源像素传感器单元，具有快速的NPN发射极跟随器读数

    公开(公告)号：US06297492B1

    公开(公告)日：2001-10-02

    申请号：US09003477

    申请日：1998-01-06

    申请人： Lawrence T. Clark

    发明人： Lawrence T. Clark

    IPC分类号： H01J4014

    CPC分类号： H01L27/14609 ,  H04N5/3745 ,  H04N5/37452

    摘要： A read out circuit is provided. The read out circuit includes an emitter follower circuit (EFC) that receives information indicative of an intensity of light detected by a pixel of an active pixel sensor array. The EFC drives a value related to the information to a read out device when the pixel is accessed.

    摘要翻译： 提供读出电路。 读出电路包括射极跟随器电路（EFC），其接收指示由有源像素传感器阵列的像素检测到的光的强度的信息。 当访问像素时，EFC将驱动与读出设备相关的信息值。

    Well to substrate photodiode for use in a CMOS sensor on a salicide process
    42.
    发明授权
    Well to substrate photodiode for use in a CMOS sensor on a salicide process 失效
    对于在自对准硅化物工艺中的CMOS传感器中使用的衬底光电二极管

    公开(公告)号：US6040592A

    公开(公告)日：2000-03-21

    申请号：US873987

    申请日：1997-06-12

    申请人： Bart McDaniel ,  Mark A. Beiley ,  Lawrence T. Clark ,  Eric J. Hoffman ,  Edward J. Bawolek

    发明人： Bart McDaniel ,  Mark A. Beiley ,  Lawrence T. Clark ,  Eric J. Hoffman ,  Edward J. Bawolek

    IPC分类号： H04N1/028 ,  C07D491/048 ,  H01L27/146 ,  H01L31/10 ,  H01L31/113 ,  H01L31/068 ,  H01L31/0352

    CPC分类号： H01L27/14643 ,  H01L27/14609 ,  H01L31/1136

    摘要： An image sensor having a well-to-substrate diode as the photodetector. In a preferred embodiment, a modern salicided (CMOS) process is utilized to manufacture the image sensor. The field oxide region above the diode junction is transparent to visible light, thus allowing the photodiode competitive quantum efficiency as compared to devices having source/drain diffusion-to-substrate photodiodes fabricated on a non-salicided process. The photodiode can be integrated as part of a sensor array with digital circuitry using a relatively unmodified digital CMOS process. Furthermore, the structure allows the optical properties of the photodiode to be engineered by modifying the well without deleterious effects, to approximate a first order, on the characteristics of a FET built in another identical well.

    摘要翻译： 一种具有良好对衬底二极管作为光电检测器的图像传感器。 在优选实施例中，利用现代的水银（CMOS）工艺来制造图像传感器。 二极管结上方的场氧化物区域对于可见光是透明的，因此与在非水银工艺上制造的源/漏扩散至衬底光电二极管的器件相比，光电二极管的竞争量子效率。 光电二极管可以作为具有使用相对未修改的数字CMOS工艺的数字电路的传感器阵列的一部分进行集成。 此外，该结构允许光电二极管的光学性质通过修改阱而不会对其内置于另一相同阱中的FET的特性产生有害影响，即接近于一阶。

    Large fan-in, dynamic, bicmos logic gate
    43.
    发明授权
    Large fan-in, dynamic, bicmos logic gate 失效
    大型扇形，动态，双向逻辑门

    公开(公告)号：US5399918A

    公开(公告)日：1995-03-21

    申请号：US129664

    申请日：1993-09-30

    申请人： Gregory F. Taylor ,  Lawrence T. Clark

    发明人： Gregory F. Taylor ,  Lawrence T. Clark

    IPC分类号： G06F15/78 ,  H03K19/003 ,  H03K19/08 ,  H03K19/0944 ,  H03K19/02 ,  H03K17/16

    CPC分类号： H03K19/00346 ,  H03K19/09448

    摘要： A highly reliable, large fan-in, high speed, BiCMOS circuit. The amount of MOS transistor parasitic capacitance appearing on the output line of the circuit is reduced by adding only emitter capacitance of bipolar transistors to the output line for each input to the basic logic circuit. Circuitry is provided to raise the base voltage of a reverse biased bipolar transistors to reduce or eliminate the reverse bias.

    摘要翻译： 高可靠性，大型风扇，高速BiCMOS电路。 通过向基本逻辑电路的每个输入添加双极晶体管的发射极电容，减少了出现在电路的输出线上的MOS晶体管寄生电容的量。 提供电路以提高反向偏置双极晶体管的基极电压，以减少或消除反向偏置。

    Digital phase-locked loop filter
    44.
    发明授权
    Digital phase-locked loop filter 失效
    数字锁相环滤波器

    公开(公告)号：US5272730A

    公开(公告)日：1993-12-21

    申请号：US811513

    申请日：1991-12-20

    申请人： Lawrence T. Clark

    发明人： Lawrence T. Clark

    IPC分类号： G11B20/10 ,  H03L7/089 ,  H03D3/24

    CPC分类号： H03L7/089 ,  G11B20/10212

    摘要： A digital filter for a phase-locked loop operates to compare the bit values of the data represented by the incoming pulse stream with patterns in that pulse stream known to produce bit shifting (either early or late). The bit shift caused by physical interaction of bits encoded on computer diskettes or the like always is predictable, in accordance with the pattern of previous bits, the current bit and the next bit. This information is processed by a logic circuit to predict which pulses in the incoming stream of data pulses are shifted. A signal is produced each time a predicted shifted pulse is determined; and this signal is utilized in conjunction with the output of the phase difference counter in the digital phase-locked loop to permit the phase of the controlled oscillator to be adjusted at each unshifted bit in a normal manner, and compensated for adjustment in a modified manner as a result of the prediction of the shifted pulses.

    摘要翻译： 用于锁相环的数字滤波器用于将由输入脉冲流表示的数据的比特值与已知产生比特移位（早或晚）的脉冲流中的模式进行比较。 根据先前位的模式，当前位和下一位，总是可以预测由计算机软盘等上编码的位的物理交互引起的位移。 该信息由逻辑电路处理以预测数据脉冲的输入流中的哪些脉冲被移位。 每当确定预测的移位脉冲时产生信号; 并且该信号与数字锁相环中的相位差计数器的输出一起使用，以允许以正常方式在每个未移位位调整受控振荡器的相位，并以修改的方式进行调整 作为移位脉冲的预测的结果。

    "> Pipelined
    45.
    发明授权
    Pipelined "best match" content addressable memory 失效
    流水线“最佳匹配”内容可寻址内存

    公开(公告)号：US4897814A

    公开(公告)日：1990-01-30

    申请号：US202376

    申请日：1988-06-06

    申请人： Lawrence T. Clark

    发明人： Lawrence T. Clark

    IPC分类号： G06F17/30

    CPC分类号： G06F17/30982

    摘要： A memory system for rapidly choosing a stored item which most closely matches a given input is having a unique memory architecture capable of returning the item stored which most closely correlates to the input. The architecture represents a departure from previous digital content-addressable memories (CAM's) in that it is capable of returning the stored data which most closley resembles the input data rapidly. In addition, a measure of the quality of the selected (best matching) memory is generated. The architecture is capable of significant data throughput rates due to pipelining, and is amenable to implementation using conventional digital VLSI fabrication processes.

    摘要翻译： 用于快速选择与给定输入最接近匹配的存储项目的存储器系统具有能够返回与输入最密切相关的存储的项目的唯一存储器架构。 该架构代表了与以前的数字内容可寻址存储器（CAM）的偏离，因为它能够快速地返回最接近的输入数据的存储数据。 此外，产生所选（最佳匹配）存储器的质量的量度。 该架构由于流水线而具有显着的数据吞吐率，并且适用于使用常规数字VLSI制造工艺的实现。

    Secure true random number generation using 1.5-T transistor flash memory
    46.
    发明授权
    Secure true random number generation using 1.5-T transistor flash memory 有权

    公开(公告)号：US10078494B2

    公开(公告)日：2018-09-18

    申请号：US15276087

    申请日：2016-09-26

    申请人： Lawrence T. Clark ,  James Adams ,  Keith E. Holbert

    发明人： Lawrence T. Clark ,  James Adams ,  Keith E. Holbert

    IPC分类号： G06F7/58

    CPC分类号： G06F7/588

    摘要： This disclosure relates generally to physically unclonable function (PUF) circuitry along with methods of generating numbers. In one embodiment, the PUF circuitry includes a memory, a memory control circuitry, and whitening circuitry. To reduce or eliminate the systematic bias from the array, whitening circuitry is configured to generate a random number comprising random number bits in response to the memory control circuit implementing at least one sequence of memory cycles on the array of the memory cells in the memory. The whitening circuitry is configured to provide the random number bits of the random number based on the variable bit states stored by the array of the memory cells. On average the whitening circuitry is configured to provide approximately half of the random number bits in the first bit state and half of random number bits in a second bit state.

    Low complexity out-of-order issue logic using static circuits
    47.
    发明授权
    Low complexity out-of-order issue logic using static circuits 有权

    公开(公告)号：US09740494B2

    公开(公告)日：2017-08-22

    申请号：US13459964

    申请日：2012-04-30

    申请人： Lawrence T. Clark ,  Siddhesh Mhambrey ,  Satendra Kumar Maurya

    发明人： Lawrence T. Clark ,  Siddhesh Mhambrey ,  Satendra Kumar Maurya

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3836 ,  G06F9/3814 ,  G06F9/3838 ,  G06F9/3851

    摘要： Instruction issue circuits are disclosed that are configured to issue multiple instructions within a superscalar pipeline of a microprocessor. The instruction issue circuit includes an instruction queue that stores instructions. A ready generation circuit is operably associated with the instruction queue and generates ready signals that indicate which instructions in the instruction queue are ready for execution. To simplify the instruction issue circuit, the instruction issue circuit has group blocks. Each group block receives a different group of the ready signals corresponding to a different group of the instructions. Each group block generates a group output indicating a group set within the corresponding group of the instructions that has a highest instruction execution priority and are ready for execution. By splitting the ready signals into groups, the groups of ready signals can be processed in parallel thereby reducing both the resulting delay and complexity of the instruction issue circuit.

    TECHNIQUES FOR GENERATING PHYSICAL LAYOUTS OF IN SILICO MULTI MODE INTEGRATED CIRCUITS
    49.
    发明申请
    TECHNIQUES FOR GENERATING PHYSICAL LAYOUTS OF IN SILICO MULTI MODE INTEGRATED CIRCUITS 有权
    用于生成硅多模式集成电路的物理层的技术

    公开(公告)号：US20150363517A1

    公开(公告)日：2015-12-17

    申请号：US14739347

    申请日：2015-06-15

    申请人： Lawrence T. Clark ,  Dan Wheeler Patterson ,  Chandarasekaran Ramamurthy ,  Srivatsan Chellappa

    发明人： Lawrence T. Clark ,  Dan Wheeler Patterson ,  Chandarasekaran Ramamurthy ,  Srivatsan Chellappa

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G06F17/5072

    摘要： This disclosure relates generally to computerized systems and methods of producing a physical representation of an in silico Integrated Circuit (IC) having an in silico Multi-Mode Redundant (MMR) pipeline circuit. An IC layout of the in silico IC is initially generated with the electronic design automation (EDA) program. Multi-Mode Redundant Self-Correcting Sequential State Element (MMRSCSSE) layouts are then rendered immotile while initial redundant Combinational Logic Circuit (CLC) layouts are removed from the IC layout after the MMRSCSSE layouts have been rendered immotile. By first placing the MMRSCSSE layouts and then rendering them immotile, the remaining logic can be placed again and optimized without compromising critical node spacing. As such, the described method provides for a more efficient way to create the IC layout of the in silico IC while maintaining critical node spacing.

    摘要翻译： 本公开一般涉及具有计算机多模冗余（MMR）流水线电路的计算机集成电路（IC）的物理表示的计算机化系统和方法。 电子计算机IC的IC布局最初是通过电子设计自动化（EDA）程序生成的。 然后，在MMRSCSSE布局变得不稳定之后，多模式冗余自校正顺序状态元素（MMRSCSSE）布局变得不可移动，而从IC布局中删除初始冗余组合逻辑电路（CLC）布局。 首先放置MMRSCSSE布局，然后使它们变得不漂亮，剩下的逻辑可以重新放置并优化，而不会影响关键的节点间距。 因此，所描述的方法提供了一种更有效的方法来创建计算机IC的IC布局，同时保持关键的节点间隔。