公开(公告)号：US08030222B2

公开(公告)日：2011-10-04

申请号：US11497036

申请日：2006-07-31

申请人： Luan Tran ,  Bill Stanton

发明人： Luan Tran ,  Bill Stanton

IPC分类号： H01L21/027

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L27/10894 ,  H01L27/11517 ,  Y10S438/942 ,  Y10S438/947

摘要： Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory devices. The portions of the lines at the periphery of the memory device are formed at an angle and are widened relative to the portions of the lines in the array region of the memory device. The widened lines allow for an increased margin of error when overlaying other features, such as landing pads, on the lines. The possibility of contacting and causing electrical shorts with adjacent lines is thus minimized. In addition, forming the portions of the lines in the periphery at an angle relative to the portions of the lines in the array regions allows the peripheral portions to be widened while also allowing multiple landing pads to be densely packed at the periphery.

摘要翻译： 提供了方法和结构，用于在将间距倍增的互连线与存储器件中的其它导电特征相接触时增加对准边缘。 存储器件周围的线的部分形成为一角度并相对于存储器件的阵列区域中的线的部分加宽。 当在线上覆盖其他特征（例如着陆垫）时，加宽的线允许增加的误差。 因此，使相邻线路接触和引起电短路的可能性被最小化。 此外，相对于阵列区域中的线的一部分以相对于周边的一部分线形成的部分允许周边部分被加宽，同时还允许多个着陆垫在周边被密集地包装。

公开(公告)号：US20110223761A1

公开(公告)日：2011-09-15

申请号：US13113468

申请日：2011-05-23

申请人： John K. Lee ,  Hyuntae Kim ,  Richard L. Stocks ,  Luan Tran

发明人： John K. Lee ,  Hyuntae Kim ,  Richard L. Stocks ,  Luan Tran

IPC分类号： H01L21/768 ,  G06F17/50

CPC分类号： H01L21/76816 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods for fabricating contacts of semiconductor device structures include forming a dielectric layer over a semiconductor substrate with active-device regions spaced at a first pitch, forming a first plurality of substantially in-line apertures over every second active-device region of the active-device regions, and forming a second plurality of substantially in-line apertures laterally offset from apertures of the first plurality over active-device regions over which apertures of the first plurality are not located. Methods for designing semiconductor device structures include forming at least two laterally offset sets of contacts over a substrate including active-device regions at a first pitch, the contacts being formed at a second pitch that is about twice the first pitch.

摘要翻译： 用于制造半导体器件结构的触点的方法包括在半导体衬底上形成介电层，所述有源器件区域以第一间距隔开，在有源器件的每个第二有源器件区域上形成第一多个基本上一字排列的孔 并且形成第二多个基本上在线的孔，所述第二多个基本上在线的孔横向偏离所述第一多个的主动装置区域上的所述第一多个孔的孔不在其上的位置。 设计半导体器件结构的方法包括在包括有源器件区的第一间距的衬底上形成至少两个横向偏移的触点组，所述触点以大约是第一间距的两倍的第二间距形成。

公开(公告)号：US07667234B2

公开(公告)日：2010-02-23

申请号：US11811502

申请日：2007-06-11

申请人： Hongmei Wang ,  Chandra Mouli ,  Luan Tran

发明人： Hongmei Wang ,  Chandra Mouli ,  Luan Tran

IPC分类号： H01L29/04

CPC分类号： H01L21/84 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/10891 ,  H01L27/1203 ,  H01L29/41758 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/7854 ,  Y10S257/905 ,  Y10S257/907 ,  Y10S438/982

摘要： A memory array having decreased cell sizes and having transistors with increased channel widths. More specifically, pillars are formed in a substrate such that sidewalls are exposed. The sidewalls of the pillars and the top surface of the pillars are covered with a gate oxide and a polysilicon layer to form a channel through the pillars. The current path through the channel is approximately equal to twice the height of the pillar plus the width of the pillar. The pillars are patterned to form non-linear active area lines having angled segments. The polysilicon layer is patterned to form word lines that intersect the active area lines at the angled segments.

摘要翻译： 具有减小的单元尺寸并且具有增加的沟道宽度的晶体管的存储器阵列。 更具体地，在衬底中形成支柱，使得侧壁被暴露。 支柱的侧壁和柱的顶表面被栅极氧化物和多晶硅层覆盖以形成通过柱的通道。 通过通道的电流通道大约等于柱的高度加上柱的宽度的两倍。 支柱被图案化以形成具有成角度段的非线性有源面积线。 将多晶硅层图案化以形成与成角度段的有源区域线相交的字线。

公开(公告)号：US20090242961A1

公开(公告)日：2009-10-01

申请号：US12059024

申请日：2008-03-31

申请人： Sanh Tang ,  Max Hineman ,  Kyu Min ,  Luan Tran

发明人： Sanh Tang ,  Max Hineman ,  Kyu Min ,  Luan Tran

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11568

摘要： A memory device comprising one or more recessed channel select gates and at least one charge trapping layer.

摘要翻译： 一种存储器件，包括一个或多个凹陷沟道选择栅极和至少一个电荷俘获层。

公开(公告)号：US07545009B2

公开(公告)日：2009-06-09

申请号：US11072159

申请日：2005-03-04

申请人： Ravi Iyer ,  Yongjun Jeff Hu ,  Luan Tran ,  Brent Gilgen

发明人： Ravi Iyer ,  Yongjun Jeff Hu ,  Luan Tran ,  Brent Gilgen

IPC分类号： H01L29/78

CPC分类号： H01L21/76846 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/7687 ,  H01L21/76889 ,  H01L23/485 ,  H01L27/10855 ,  H01L28/84 ,  H01L28/90 ,  H01L29/456 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

摘要： Various embodiments of the invention described herein reduce contact resistance to a silicon-containing material using a first refractory metal material overlying the silicon-containing material and a second refractory metal material overlying the first refractory metal material. Each refractory metal material is a conductive material containing a refractory metal and an impurity. The first refractory metal material is a metal-rich material, containing a level of its impurity at less than a stoichiometric level. The second refractory metal material has a lower affinity for the impurities than does the first refractory metal material. The second refractory metal material can thus serve as an impurity donor during an anneal or other exposure to heat. This net migration of the impurities to the first refractory metal material limits growth of a metal silicide interface between the first refractory metal material and the underlying silicon-containing material, thereby providing ohmic contact with attendant thermal tolerance.

摘要翻译： 使用覆盖含硅材料的第一耐火金属材料和覆盖第一难熔金属材料的第二难熔金属材料来降低与含硅材料的接触电阻。 每种难熔金属材料是含有难熔金属和杂质的导电材料。 第一难熔金属材料是富含金属的材料，其含量低于化学计量水平的杂质。 与第一难熔金属材料相比，第二难熔金属材料对杂质的亲和力较低。 因此，第二难熔金属材料可以在退火或其它暴露于热的过程中用作杂质供体。 这种杂质向第一难熔金属材料的净迁移限制了第一难熔金属材料和下面的含硅材料之间的金属硅化物界面的生长，从而提供与耐热性的欧姆接触。

公开(公告)号：US07332767B2

公开(公告)日：2008-02-19

申请号：US11286670

申请日：2005-11-23

申请人： Hongmei Wang ,  Chandra Mouli ,  Luan Tran

发明人： Hongmei Wang ,  Chandra Mouli ,  Luan Tran

IPC分类号： H01L29/788

CPC分类号： H01L21/84 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/10891 ,  H01L27/1203 ,  H01L29/41758 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/7854 ,  Y10S257/905 ,  Y10S257/907 ,  Y10S438/982

摘要： A memory device having decreased cell size and having transistors with increased channel widths. The sidewalls of the pillars and the top surface of the pillars are covered with a gate oxide and a conductive layer to form a channel through the pillars. The current path through the channel is approximately equal to twice the height of the pillar plus the width of the pillar. The pillars are patterned to form non-linear active area lines having angled segments. The conductive layer is patterned to from word lines that intersect the active area lines at the angled segments.

摘要翻译： 具有减小的单元尺寸并且具有增加的沟道宽度的晶体管的存储器件。 支柱的侧壁和柱的顶表面被栅极氧化物和导电层覆盖以形成通过柱的通道。 通过通道的电流通道大约等于柱的高度加上柱的宽度的两倍。 支柱被图案化以形成具有成角度段的非线性有源面积线。 导电层被图案化以形成与成角度段的有源区域线相交的字线。

公开(公告)号：US07300839B2

公开(公告)日：2007-11-27

申请号：US10612333

申请日：2003-07-02

申请人： Luan Tran

发明人： Luan Tran

IPC分类号： H01L21/00

CPC分类号： H01L27/10888 ,  H01L27/0207 ,  H01L27/10855 ,  H01L27/10885 ,  Y10S257/905 ,  Y10S257/907 ,  Y10S257/908

摘要： A memory cell having a bit line contact is provided. The memory cell may be a 6F2 memory cell. The bit line contact may have a contact hole bounded by insulating sidewalls, and the contact hole may be partially or completely filled with a doped polysilicon plug. The doped polysilicon plug may have an upper plug surface profile that is substantially free of concavities or substantially convex. Similarly, a storage node contact may comprise a doped polysilicon plug having an upper plug surface profile that is substantially free of concavities or that is substantially convex. Additionally, a semiconductor device having a conductive contact comprising a polysilicon plug may is provided. The plug may contact a capacitor structure.

摘要翻译： 提供具有位线接触的存储单元。 存储单元可以是6F 2存储单元。 位线接触可以具有由绝缘侧壁界定的接触孔，并且接触孔可以部分地或完全地被掺杂的多晶硅插塞填充。 掺杂多晶硅插塞可以具有基本上没有凹面或基本上凸起的上部插塞表面轮廓。 类似地，存储节点接触件可以包括具有基本上没有凹部或基本上是凸起的上插塞表面轮廓的掺杂多晶硅插塞。 此外，可以提供具有包括多晶硅插塞的导电接触的半导体器件。 插头可以接触电容器结构。

公开(公告)号：US07294545B2

公开(公告)日：2007-11-13

申请号：US11041357

申请日：2005-01-24

申请人： Luan Tran

发明人： Luan Tran

IPC分类号： H01L21/8242

CPC分类号： H01L27/10888 ,  H01L21/76879 ,  H01L27/10814 ,  H01L27/10855

摘要： A memory cell having a bit line contact is provided. The memory cell may be a 6F2 memory cell. The bit line contact may have a contact hole bounded by insulating sidewalls, and the contact hole may be partially or completely filled with a doped polysilicon plug. The doped polysilicon plug may have an upper plug surface profile that is substantially free of concavities or substantially convex. Similarly, a storage node contact may comprise a doped polysilicon plug having an upper plug surface profile that is substantially free of concavities or that is substantially convex. Additionally, a semiconductor device having a conductive contact comprising a polysilicon plug may is provided. The plug may contact a capacitor structure.

摘要翻译： 提供具有位线接触的存储单元。 存储单元可以是6F 2存储单元。 位线接触可以具有由绝缘侧壁界定的接触孔，并且接触孔可以部分地或完全地被掺杂的多晶硅插塞填充。 掺杂多晶硅插塞可以具有基本上没有凹面或基本上凸起的上部插塞表面轮廓。 类似地，存储节点接触件可以包括具有基本上没有凹部或基本上是凸起的上插塞表面轮廓的掺杂多晶硅插塞。 另外，可以提供具有包括多晶硅插头的导电接触的半导体器件。 插头可以接触电容器结构。

公开(公告)号：US20070241395A1

公开(公告)日：2007-10-18

申请号：US11811502

申请日：2007-06-11

申请人： Hongmei Wang ,  Chandra Mouli ,  Luan Tran

发明人： Hongmei Wang ,  Chandra Mouli ,  Luan Tran

IPC分类号： H01L29/94

CPC分类号： H01L21/84 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/10891 ,  H01L27/1203 ,  H01L29/41758 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/7854 ,  Y10S257/905 ,  Y10S257/907 ,  Y10S438/982

摘要： A memory array having decreased cell sizes and having transistors with increased channel widths. More specifically, pillars are formed in a substrate such that sidewalls are exposed. The sidewalls of the pillars and the top surface of the pillars are covered with a gate oxide and a polysilicon layer to form a channel through the pillars. The current path through the channel is approximately equal to twice the height of the pillar plus the width of the pillar. The pillars are patterned to form non-linear active area lines having angled segments. The polysilicon layer is patterned to form word lines that intersect the active area lines at the angled segments.

公开(公告)号：US20060264001A1

公开(公告)日：2006-11-23

申请号：US11497036

申请日：2006-07-31

申请人： Luan Tran ,  Bill Stanton

发明人： Luan Tran ,  Bill Stanton

IPC分类号： H01L21/76 ,  H01L23/544

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L27/10894 ,  H01L27/11517 ,  Y10S438/942 ,  Y10S438/947

摘要： Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory devices. The portions of the lines at the periphery of the memory device are formed at an angle and are widened relative to the portions of the lines in the array region of the memory device. The widened lines allow for an increased margin of error when overlaying other features, such as landing pads, on the lines. The possibility of contacting and causing electrical shorts with adjacent lines is thus minimized. In addition, forming the portions of the lines in the periphery at an angle relative to the portions of the lines in the array regions allows the peripheral portions to be widened while also allowing multiple landing pads to be densely packed at the periphery.

摘要翻译： 提供了方法和结构，用于在将间距倍增的互连线与存储器件中的其它导电特征相接触时增加对准边缘。 存储器件周围的线的部分形成为一角度并相对于存储器件的阵列区域中的线的部分加宽。 当在线上覆盖其他特征（例如着陆垫）时，加宽的线允许增加的误差。 因此，使相邻线路接触和引起电短路的可能性被最小化。 此外，相对于阵列区域中的线的一部分以相对于周边的一部分线形成的部分允许周边部分被加宽，同时还允许多个着陆垫在周边被密集地包装。