公开(公告)号：US11451493B2

公开(公告)日：2022-09-20

申请号：US17142366

申请日：2021-01-06

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Gal Yefet ,  Daniel Marcovitch ,  Roee Moyal ,  Ariel Shahar ,  Gil Bloch ,  Lior Narkis

IPC: H04N21/238 ,  H04L49/901 ,  H04L41/0604 ,  H04L49/253 ,  H04L49/9005

Abstract: A network adapter includes a network interface, a host interface and processing circuitry. The network interface connects to a communication network for communicating with remote targets. The host interface connects to a host that accesses a Multi-Channel Send Queue (MCSQ) storing Work Requests (WRs) originating from client processes running on the host. The processing circuitry is configured to retrieve WRs from the MCSQ and distribute the WRs among multiple Send Queues (SQs) accessible by the processing circuitry.

公开(公告)号：US11438266B2

公开(公告)日：2022-09-06

申请号：US16780940

申请日：2020-02-04

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Avi Urman ,  Lior Narkis ,  Noam Bloch

IPC: H04L45/74 ,  G06F13/42 ,  H04L69/22

Abstract: A communication apparatus includes a host interface, connected to a peripheral component bus so as to communicate with a CPU and a memory of a host computer. A network interface is connected to a network. Packet processing circuitry is configured to receive from a first interface a data packet including a set of one or more headers that include header fields having respective values, to identify, responsively to at least one of the header fields, a corresponding entry in a header modification table that specifies a header modification operation, to modify the set of headers in accordance with the header modification operation, to check whether the entry specifies an additional header modification operation, to output the modified set of headers if the entry does not specify an additional header modification operation, and, if the entry specifies an additional header modification operation, to feed-back the modified set of headers.

公开(公告)号：US11258885B2

公开(公告)日：2022-02-22

申请号：US16708470

申请日：2019-12-10

Applicant: Mellanox Technologies, Ltd.

Inventor： Avi Urman ,  Lior Narkis ,  Noam Bloch

IPC: H04L29/06 ,  G06F9/455 ,  H04L12/46 ,  H04L12/24 ,  H04L29/08 ,  H04L69/22 ,  H04L41/00 ,  H04L67/568

Abstract: One embodiment includes a network device, including hardware parsers to receive data of a header section of a packet, the header section including respective headers, parser configuration registers to store a default parsing configuration data set, wherein at least one of the hardware parsers is configured to parse at least one of the headers responsively to the default parsing configuration data set, yielding first parsed data, a packet processing engine to select a selected parsing configuration data set from a selection of parsing configuration data sets responsively to the first parsed data, cause loading of the selected parsing configuration data set into the parser configuration registers, and wherein ones of the hardware parsers are configured to parse respective ones of the headers responsively to the selected parsing configuration data set, yielding second parsed data, and process the packet responsively to the second parsed data.

公开(公告)号：US20210385169A1

公开(公告)日：2021-12-09

申请号：US17409625

申请日：2021-08-23

Applicant: Mellanox Technologies Ltd.

Inventor： Avi Urman ,  Lior Narkis ,  Gil Kremer ,  Saar Tarnopolsky ,  Dotan David Levi

IPC: H04L12/823 ,  H04L29/06 ,  H04L12/707 ,  H04L12/815

Abstract: Apparatuses, systems, and techniques to eliminate redundant data packets. In at least one embodiment, a communication apparatus generates redundant data packets, and sends them in multiple packet streams. In at least one embodiment, a communication apparatus eliminates redundant data packets from received packet streams.

公开(公告)号：US10547553B2

公开(公告)日：2020-01-28

申请号：US15996548

申请日：2018-06-04

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Guy Shattah ,  Ron Efraim ,  Lior Narkis

IPC: H04L29/06 ,  H04L12/851 ,  H04L12/931 ,  H04L12/801

Abstract: A mechanism is provided for partial offload of connection tracking from a host processor to a network interface device. Software running in the host processor is used for connection establishment. After a connection has been established the software initializes and transfers flow-control to the network interface device. Thereafter, the network interface device continues transferring packets to the destination, while the software in the host processor monitors the flow. If the connection has been terminated or has expired flow control reverts to the software. Modes of operation are provided for network interface devices with and without a specific connection-tracking module.

公开(公告)号：US10462060B2

公开(公告)日：2019-10-29

申请号：US15896128

申请日：2018-02-14

Applicant: Mellanox Technologies, Ltd.

Inventor： Jacob Ruthstein ,  David Mozes ,  Dror Bohrer ,  Ariel Shahar ,  Lior Narkis ,  Noam Bloch

IPC: H04L12/851 ,  H04L12/26 ,  H04L12/801

Abstract: Packet flows received in a data network are assigned to respective entries of a database. During an accumulation interval byte counts of the assigned packet flows are accumulated in the respective database entries. The packet flows are classified as elephant flows when differences between the byte counts and a reference byte count exceed a threshold and are reported after expiration of the accumulation interval.

公开(公告)号：US20190140979A1

公开(公告)日：2019-05-09

申请号：US16012826

申请日：2018-06-20

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan Levi ,  Liran Liss ,  Haggai Eran ,  Noam Bloch ,  Idan Burstein ,  Lior Narkis ,  Avraham Ganor

IPC: H04L12/933 ,  G06F9/455 ,  G06F13/40

Abstract: A network interface controller that is connected to a host and a packet communications network. The network interface controller includes electrical circuitry configured as a packet processing pipeline with a plurality of stages. It is determined in the network interface controller that at least a portion of the stages of the pipeline are acceleration-defined stages. Packets are processed in the pipeline by transmitting data to an accelerator from the acceleration-defined stages, performing respective acceleration tasks on the transmitted data in the accelerator, and returning processed data from the accelerator to receiving stages of the pipeline.

公开(公告)号：US20190089679A1

公开(公告)日：2019-03-21

申请号：US15706713

申请日：2017-09-17

Applicant: Mellanox Technologies, Ltd.

Inventor： Omri Kahalon ,  Lior Narkis ,  Muhamad Grefat

IPC: H04L29/06 ,  H04L12/813

Abstract: Network interface apparatus includes packet processing circuitry, comprising hardware logic coupled between a network interface and a host interface for connection to a host processor. The hardware logic accesses a list of active connections established between the local processes running on the host processor and corresponding processes on other computers on the network and maintains context information with respect to each of the active connections. Upon receiving a packet from the network having a header identifying the packet as having been transmitted to a local process in accordance with a predefined transport protocol, the hardware logic checks the list to find a connection to which the packet belongs and upon finding the connection, verifies that the packet conforms to the respective state indicated by the context information for the connection and, if so, updates the context information and passes the packet to the local process.

公开(公告)号：US20190081904A1

公开(公告)日：2019-03-14

申请号：US15701459

申请日：2017-09-12

Applicant: Mellanox Technologies, Ltd.

Inventor： Dror Bohrer ,  Noam Bloch ,  Lior Narkis ,  Hillel Chapman ,  Gilad Hammer

IPC: H04L12/863 ,  H04L12/813 ,  G06F9/455

CPC classification number: H04L47/6235 ,  G06F9/45558 ,  G06F2009/45595 ,  H04L45/74 ,  H04L47/20 ,  H04L49/70

Abstract: Network interface apparatus includes a host interface and a network interface, which receives packets in multiple packet flows destined for one or more virtual machines running on a host processor. Packet processing circuitry receives a first instruction from the host processor to offload preprocessing of the data packets in a specified flow in accordance with a specified rule, and initiates preprocessing of the data packets while writing one or more initial data packets from the specified flow to a temporary buffer. Upon subsequently receiving a second instruction to enable the specified rule, the initial data packets are delivered from the temporary buffer, after preprocessing by the packet processing circuitry, directly to a virtual machine to which the specified flow is destined, followed by preprocessing and delivery of subsequent data packets in the specified flow to the virtual machine.