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    PHYSICAL LAYER SYNCHRONIZATION
    42.
    发明申请
    PHYSICAL LAYER SYNCHRONIZATION 有权

    公开(公告)号：US20240372691A1

    公开(公告)日：2024-11-07

    申请号：US18367383

    申请日：2023-09-12

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Natan Manevich ,  Dotan David Levi ,  Wojciech Wasko ,  Maciek Machnikowski

    IPC: H04L7/00

    Abstract: A system includes a device including a transmitter associated with a link coupled to the device. The device is to receive from an application layer of the device, a first bitstream for transmission. The device is to encode the first bitstream into one or more blocks and transmit the one or more data blocks via the link. The device is also to receive a second bitstream to be transmitted. The device is to encode the second bitstream into a control block and transmit the control block via the link. The control block includes a first portion of bits corresponding to a header indicating the control block includes the second bitstream and a second portion of bits including the second bitstream.

    SYNTONIZATION THROUGH PHYSICAL LAYER OF INTERCONNECTS
    45.
    发明公开
    SYNTONIZATION THROUGH PHYSICAL LAYER OF INTERCONNECTS 审中-公开

    公开(公告)号：US20240031124A1

    公开(公告)日：2024-01-25

    申请号：US17868841

    申请日：2022-07-20

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Dotan David Levi ,  Wojciech Wasko ,  Natan Manevich

    IPC: H04L7/027 ,  H04L12/40

    CPC classification number: H04L7/027 ,  H04L12/40

    Abstract: In one embodiment, a clock syntonization system includes a first compute node including a first physical hardware clock to operate at a first clock frequency, a second compute node, and an interconnect data bus to transfer data from the first compute node at a data rate indicative of the first clock frequency of the first physical hardware clock, and wherein the second compute node includes clock synchronization circuitry to derive a second clock frequency from the data rate of the transferred data, and provide a clock signal at the derived second clock frequency.

    Scalable Boundary Clock
    47.
    发明公开
    Scalable Boundary Clock 审中-公开

    公开(公告)号：US20230367358A1

    公开(公告)日：2023-11-16

    申请号：US17867779

    申请日：2022-07-19

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Natan Manevich ,  Dotan David Levi ,  Wojciech Wasko ,  Ariel Almog ,  Bar Shapira

    IPC: G06F1/12 ,  G06F1/10 ,  G06F1/06

    CPC classification number: G06F1/12 ,  G06F1/10 ,  G06F1/06

    Abstract: In one embodiment, a synchronized communication system includes a first network device and a second network device, wherein the first network device includes a first physical hardware clock, and is configured to recover a reference clock time from packets received from a remote clock, find a clock differential between a clock time output by the first physical hardware clock and the recovered reference clock time, provide a control signal to the second network device responsively to the clock differential, and the second network device includes a second physical hardware clock, and is configured to adjust a clock time output by the second physical hardware clock responsively to the control signal.

    TIMESTAMP CONTROL LOOP
    49.
    发明申请
    TIMESTAMP CONTROL LOOP 有权

    公开(公告)号：US20250047402A1

    公开(公告)日：2025-02-06

    申请号：US18229074

    申请日：2023-08-01

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Yam Gellis ,  Oren Matus ,  Liron Mula ,  Natan Manevich ,  Hillel Chapman ,  Dotan David Levi

    IPC: H04J3/06

    Abstract: A device includes a receiver including a timestamp generator to update timestamps at a first rate. The receiver is to estimate a first time for receiving a signal, wherein the signal is associated with a synchronization operation. The receiver is further to receive the signal at a second time. The receiver is further to determine a difference between the second time and the first time, wherein the difference is associated with an error of the timestamp generator of the receiver. The receiver can also adjust the first rate to a second rate at which to update the timestamps by the timestamp generator, responsive to determining the difference between the first time and the second time.

    Clock adjustment holdover
    50.
    发明授权
    Clock adjustment holdover 有权

    公开(公告)号：US12216489B2

    公开(公告)日：2025-02-04

    申请号：US18111916

    申请日：2023-02-21

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Wojciech Wasko ,  Dotan David Levi ,  Natan Manevich ,  Maciek Machnikowski

    IPC: G06F1/12 ,  G06F1/08 ,  G06F1/14

    Abstract: In one embodiment, a clock synchronization system includes clock circuitry to maintain a clock running at a clock frequency, a clock controller, and a processor to execute software to generate clock update commands and provide the clock update commands to the clock controller, wherein the clock controller is configured to apply the clock update commands to the clock, store a holdover frequency command to maintain the clock during a failure of the clock update commands, apply the holdover frequency command to the clock responsively to detecting the failure.

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