公开(公告)号：US20210280225A1

公开(公告)日：2021-09-09

申请号：US17212708

申请日：2021-03-25

Applicant: Micron Technology, Inc.

Inventor： Robert Nasry Hasbun ,  Timothy M. Hollis ,  Jeffrey P. Wright ,  Dean D. Gans

IPC: G11C7/10 ,  G06F1/3234 ,  G06F13/42 ,  G11C11/22

Abstract: Methods, systems, and devices for multiple concurrent modulation schemes in a memory system are described. Techniques are provided herein to communicate data using a modulation scheme having at least three levels and using a modulation scheme having at least two levels within a common system or memory device. Such communication with multiple modulation schemes may be concurrent. The modulated data may be communicated to a memory die through distinct signal paths that may correspond to a particular modulation scheme. An example of a modulation scheme having at least three levels may be pulse amplitude modulation (PAM) and an example of a modulation scheme having at least two levels may be non-return-to-zero (NRZ).

公开(公告)号：US10978116B2

公开(公告)日：2021-04-13

申请号：US16530525

申请日：2019-08-02

Applicant: Micron Technology, Inc.

Inventor： Robert Nasry Hasbun ,  Timothy M. Hollis ,  Jeffrey P. Wright ,  Dean D. Gans

IPC: G06F7/10 ,  G11C7/10 ,  G06F1/3234 ,  G06F13/42 ,  G11C11/22 ,  G11C11/4093

Abstract: Methods, systems, and devices for multiple concurrent modulation schemes in a memory system are described. Techniques are provided herein to communicate data using a modulation scheme having at least three levels and using a modulation scheme having at least two levels within a common system or memory device. Such communication with multiple modulation schemes may be concurrent. The modulated data may be communicated to a memory die through distinct signal paths that may correspond to a particular modulation scheme. An example of a modulation scheme having at least three levels may be pulse amplitude modulation (PAM) and an example of a modulation scheme having at least two levels may be non-return-to-zero (NRZ).

公开(公告)号：US10904052B2

公开(公告)日：2021-01-26

申请号：US16419870

申请日：2019-05-22

Applicant: Micron Technology, Inc.

Inventor： Robert Nasry Hasbun ,  Timothy M. Hollis ,  Jeffrey P. Wright ,  Dean D. Gans

IPC: H04L27/04 ,  G06F13/38 ,  H04L27/06 ,  H04L27/02 ,  H04L25/49 ,  G06F13/16 ,  G11C5/06 ,  G11C7/10

Abstract: Methods, systems, and devices for multiplexing distinct signals on a single pin of a memory device are described. Techniques are described herein to multiplex data using a modulation scheme having at least three levels. The modulated data may be communicated to multiple memory dies over a shared bus. Each of the dies may include a same or different type of memory cell and, in some examples, a multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the modulated signal may be configured to represent a plurality of bits of data.

公开(公告)号：US10861519B2

公开(公告)日：2020-12-08

申请号：US16375764

申请日：2019-04-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： William F. Jones ,  Jeffrey P. Wright

IPC: G11C7/00 ,  G11C8/10 ,  G11C11/406 ,  G11C11/408 ,  G11C17/16 ,  G11C17/18 ,  G11C29/00

Abstract: Apparatuses and methods for targeted row refreshes are disclosed herein. In an example apparatus, a predecoder receives a target row address and determines whether a target row of memory associated with the target row address is a primary or a redundant row of memory. The predecoder is further configured to cause one or more rows of memory physically adjacent the primary row of memory to be refreshed if the primary row is the target row or one or more rows of memory physically adjacent the redundant row of memory to be refreshed if the redundant row of memory is the target row of memory.

公开(公告)号：US10600472B2

公开(公告)日：2020-03-24

申请号：US16105889

申请日：2018-08-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Scott J. Derner ,  Huy T. Vo ,  Patrick Mullarkey ,  Jeffrey P. Wright ,  Michael A. Shore

IPC: G11C11/4091 ,  G11C11/406 ,  G11C11/4072 ,  G11C11/4094 ,  G11C11/4096

Abstract: Systems and methods are provided for implementing an array reset mode. An example system includes at least one mode register configured to enable an array reset mode, a memory cell array including one or more sense amplifiers, and control logic. Each of the one or more sense amplifier may include at least a first terminal coupled to a first bit line and a second terminal coupled to a second bit line. The control logic may be coupled to the memory cell array, and in communication with the at least one mode register. The control logic may be configured to drive, in response to array reset mode being enabled, each of the first and second terminals of the sense amplifier to a bit-line precharge voltage that corresponds to a bit value to be written to respective memory cells associated with each of the first and second bit lines.

公开(公告)号：US10446198B2

公开(公告)日：2019-10-15

申请号：US15977815

申请日：2018-05-11

Applicant: Micron Technology, Inc.

Inventor： Robert Nasry Hasbun ,  Timothy M. Hollis ,  Jeffrey P. Wright ,  Dean D. Gans

IPC: G11C7/10 ,  G06F1/3234 ,  G06F13/42 ,  G11C11/22 ,  G11C11/4093

Abstract: Methods, systems, and devices for multiple concurrent modulation schemes in a memory system are described. Techniques are provided herein to communicate data using a modulation scheme having at least three levels and using a modulation scheme having at least two levels within a common system or memory device. Such communication with multiple modulation schemes may be concurrent. The modulated data may be communicated to a memory die through distinct signal paths that may correspond to a particular modulation scheme. An example of a modulation scheme having at least three levels may be pulse amplitude modulation (PAM) and an example of a modulation scheme having at least two levels may be non-return-to-zero (NRZ).

公开(公告)号：US20190102330A1

公开(公告)日：2019-04-04

申请号：US15977818

申请日：2018-05-11

Applicant: Micron Technology, Inc.

Inventor： Robert Nasry Hasbun ,  Timothy M. Hollis ,  Jeffrey P. Wright ,  Dean D. Gans

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  G11C5/02 ,  G11C5/06

Abstract: Methods, systems, and devices for communicating data with stacked memory dies are described. A first semiconductor die may communicate with an external computing device using a binary-symbol signal including two signal levels representing one bit of data. Semiconductor dies may be stacked on one another and include internal interconnects (e.g., through-silicon vias) to relay an internal signal generated based on the binary-symbol signal. The internal signal may be a multi-symbol signal modulated using a modulation scheme that includes three or more levels to represent more than one bit of data. The multi-level symbol signal may simplify the internal interconnects. A second semiconductor die may be configured to receive and re-transmit the multi-level symbol signal to semiconductor dies positioned above the second semiconductor die.

公开(公告)号：US20190102298A1

公开(公告)日：2019-04-04

申请号：US15977808

申请日：2018-05-11

Applicant: Micron Technology, Inc.

Inventor： Robert Nasry Hasbun ,  Timothy M. Hollis ,  Jeffrey P. Wright ,  Dean D. Gans

IPC: G06F12/0806

Abstract: Methods, systems, and devices that support variable modulation schemes for memory are described. A device may switch between different modulation schemes for communication based on one or more operating parameters associated with the device or a component of the device. The modulation schemes may involve amplitude modulation in which different levels of a signal represent different data values. For instance, the device may use a first modulation scheme that represents data using two levels and a second modulation scheme that represents data using four levels. In one example, the device may switch from the first modulation scheme to the second modulation scheme when bandwidth demand is high, and the device may switch from the second modulation scheme to the first modulation scheme when power conservation is in demand. The device may also, based on the operating parameter, change the frequency of the signal pulses communicated using the modulation schemes.

公开(公告)号：US20140198591A1

公开(公告)日：2014-07-17

申请号：US13744177

申请日：2013-01-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Donald M. Morgan ,  Jongtae Kwak ,  Jeffrey P. Wright

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/109 ,  H03K19/0005

Abstract: Apparatuses, sense circuits, and methods for controlling a clock signal to a clock tree is described. An example apparatus includes a consecutive write command detection circuit configured to detect whether a next write command is received within a consecutive write command period of a current write command responsive to the current write command provided at an output of the write command register. The example apparatus further includes a clock signal control circuit coupled to the consecutive write command detection circuit and configured to control a clock signal to an input/output (I/O) latch based on whether the consecutive write command detection circuit detects that the next write command is within the consecutive write command period.

Abstract translation: 描述了用于控制时钟树的时钟信号的装置，感测电路和方法。 一种示例性装置包括一个连续的写入命令检测电路，其被配置为响应于在写入命令寄存器的输出处提供的当前写入命令来检测在当前写入命令的连续写入命令周期内是否接收到下一个写入命令。 该示例设备还包括一个时钟信号控制电路，该时钟信号控制电路耦合到该连续的写命令检测电路，并且被配置为基于该连续的写入命令检测电路是否检测到下一个写入来控制到输入/输出（I / O） 命令在连续写入命令周期内。

公开(公告)号：US20250085867A1

公开(公告)日：2025-03-13

申请号：US18955719

申请日：2024-11-21

Applicant: Micron Technology, Inc.

Inventor： Bryan David Kerstetter ,  Donald M. Morgan ,  Alan J. Wilson ,  John David Porter ,  Jeffrey P. Wright

IPC: G06F3/06

Abstract: Systems, methods and apparatuses to log memory errors in memory devices that can perform wear leveling based on physical addresses used in the memory devices to address select memory cells. For example, a controller of a memory sub-system communicates with a memory device installed in the memory sub-system to access memory cells in the memory device. During the communication to access memory cells in the memory device, the controller can determine a memory error at a first address. If the controller transmits the first address to the memory device for memory access at the time of the memory error, the memory device converts the first address to a second address to perform the memory access. The controller can be configured to determine the second address and record, in an error log, the memory error in association with the second address.