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    CROSS-POINT MEMORY WITH SELF-DEFINED MEMORY ELEMENTS
    41.
    发明申请
    CROSS-POINT MEMORY WITH SELF-DEFINED MEMORY ELEMENTS 审中-公开

    公开(公告)号：US20190245007A1

    公开(公告)日：2019-08-08

    申请号：US16390996

    申请日：2019-04-22

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu

    IPC: H01L27/24 ,  H01L27/10

    CPC classification number: H01L27/2463 ,  H01L27/101 ,  H01L27/249 ,  H01L45/141 ,  H01L45/145

    Abstract: Some embodiments include a memory device having first structures arranged in a first direction and second structures arranged in a second direction. At least one structure among the first and second structures includes a semiconductor material. The second structures contact the first structures at contact locations. A region at each of the contact locations is configured as memory element to store information based on a resistance of the region. The structures can include nanowires. Other embodiments are described.

    Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices
    42.
    发明授权
    Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices 有权

    公开(公告)号：US10262734B2

    公开(公告)日：2019-04-16

    申请号：US15798166

    申请日：2017-10-30

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu

    IPC: G11C11/00 ,  G11C13/00

    Abstract: Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In one embodiment, a memory cell includes a wordline, a first bitline, a second bitline, and a memory element. The memory element is electrically connected to the wordline and selectively electrically connected to the first bitline and the second bitline. The memory element stores information via a resistive state of the memory element. The memory cell is configured to convey the resistive state of the memory element via either a first current flowing from the first bitline through the memory element to the wordline or a second current flowing from the wordline through the memory element to the second bitline.

    Semiconductor devices, memory devices, and related methods
    43.
    发明授权
    Semiconductor devices, memory devices, and related methods 有权

    公开(公告)号：US10158071B2

    公开(公告)日：2018-12-18

    申请号：US15669484

    申请日：2017-08-04

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu ,  Kunal R. Parekh

    IPC: H01L23/48 ,  H01L45/00 ,  H01L21/033 ,  H01L21/768 ,  H01L27/24 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

    Abstract: Electrical contacts may be formed by forming dielectric liners along sidewalls of a dielectric structure, forming sacrificial liners over and transverse to the dielectric liners along sidewalls of a sacrificial structure, selectively removing portions of the dielectric liners at intersections of the dielectric liners and sacrificial liners to form pores, and at least partially filling the pores with a conductive material. Nano-scale pores may be formed by similar methods. Bottom electrodes may be formed and electrical contacts may be structurally and electrically coupled to the bottom electrodes to form memory devices. Nano-scale electrical contacts may have a rectangular cross-section of a first width and a second width, each width less than about 20 nm. Memory devices may include bottom electrodes, electrical contacts having a cross-sectional area less than about 150 nm2 over and electrically coupled to the bottom electrodes, and a cell material over the electrical contacts.

    Arrays of memory cells and methods of forming an array of memory cells
    45.
    发明授权
    Arrays of memory cells and methods of forming an array of memory cells 有权

    公开(公告)号：US10068947B2

    公开(公告)日：2018-09-04

    申请号：US15375507

    申请日：2016-12-12

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu ,  Kunal R. Parekh

    IPC: H01L27/24 ,  H01L45/00

    Abstract: An array of memory cells includes buried access lines having conductively doped semiconductor material. Pillars extend elevationally outward of and are spaced along the buried access lines. The pillars individually include a memory cell. Outer access lines are elevationally outward of the pillars and the buried access lines. The outer access lines are of higher electrical conductivity than the buried access lines. A plurality of conductive vias is spaced along and electrically couple pairs of individual of the buried and outer access lines. A plurality of the pillars is between immediately adjacent of the vias along the pairs. Electrically conductive metal material is directly against tops of the buried access lines and extends between the pillars along the individual buried access lines. Other embodiments, including method, are disclosed.

    Arrays of memory cells and methods of forming an array of memory cells
    46.
    发明授权
    Arrays of memory cells and methods of forming an array of memory cells 有权

    公开(公告)号：US10014347B2

    公开(公告)日：2018-07-03

    申请号：US15852275

    申请日：2017-12-22

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu ,  Kunal R. Parekh

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/2463 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1683

    Abstract: An array of memory cells includes buried access lines having conductively doped semiconductor material. Pillars extend elevationally outward of and are spaced along the buried access lines. The pillars individually include a memory cell. Outer access lines are elevationally outward of the pillars and the buried access lines. The outer access lines are of higher electrical conductivity than the buried access lines. A plurality of conductive vias is spaced along and electrically couple pairs of individual of the buried and outer access lines. A plurality of the pillars is between immediately adjacent of the vias along the pairs. Electrically conductive metal material is directly against tops of the buried access lines and extends between the pillars along the individual buried access lines. Other embodiments, including method, are disclosed.

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