公开(公告)号：US20190332279A1

公开(公告)日：2019-10-31

申请号：US16507292

申请日：2019-07-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Timothy Hollis ,  Roy E. Greeff

IPC: G06F3/06 ,  G06F13/40 ,  G11C7/10 ,  G06F13/42

Abstract: Apparatuses and methods for multi-level communication architectures are disclosed herein. An example apparatus may include a driver circuit configured to convert a plurality of bitstreams into a plurality of multilevel signals. A count of the plurality of bitstreams is greater than count of the plurality of multilevel signals. The driver circuit further configured to drive the plurality of multilevel signals onto a plurality of signal lines using individual drivers. A driver of the individual drivers is configured to drive more than two voltages.

公开(公告)号：US10339075B2

公开(公告)日：2019-07-02

申请号：US15693027

申请日：2017-08-31

Applicant: Micron Technology, Inc.

Inventor： Roy E. Greeff ,  George Pax ,  Timothy Mowry Hollis

IPC: G06F12/00 ,  G06F13/16 ,  G06F1/10 ,  G06F13/40 ,  G06F13/42

Abstract: A computing system including multiple integrated circuit memory devices is described. One or more command and address buses are connected to the memory devices to transmit command and address signals to each memory device. Multiple clock lines are connected to the multiple memory devices in a tree structure to transmit multiple clock signals to these memory devices. The tree structure allows each distributed clock signal to be individually trained such that the multiple clock signals provide each memory device with a clock signal that is temporally aligned with the command and address signals as received by that memory device.

公开(公告)号：US20180269875A1

公开(公告)日：2018-09-20

申请号：US15941964

申请日：2018-03-30

Applicant: Micron Technology, Inc.

Inventor： Roy E. Greeff

IPC: H03K19/00 ,  H03K5/1534 ,  H03K19/003

CPC classification number: H03K19/0005 ,  H03K5/1534 ,  H03K19/00323 ,  H03K19/018521 ,  H04L25/0286

Abstract: Apparatuses and methods for partial bit de-emphasis are provided. An example apparatus includes an output driver and control circuit. The output driver includes a pull-up circuit including one or more pull-up legs, and a pull-down circuit including one or more pull-down legs. The control circuit may be coupled to the output driver and configured to receive an input signal having a first logical value and a second logical value, and in response to determining the logical transition has occurred from the second logic value to the first logic value, cause the pull-up circuit and pull-down circuit respectively to enter a first state for a duration of a first portion of a bit period and to enter a second state for a duration of a second portion of the bit period preceding the first portion.

公开(公告)号：US09196321B2

公开(公告)日：2015-11-24

申请号：US14045521

申请日：2013-10-03

Applicant: Micron Technology, Inc.

Inventor： Brian W. Huber ,  Vijay Vankayala ,  Brian Gross ,  Gary Howe ,  Roy E. Greeff

IPC: G11C7/00 ,  G11C7/02 ,  G11C5/06 ,  G11C7/10 ,  G11C29/02

CPC classification number: G11C7/02 ,  G11C5/063 ,  G11C7/1057 ,  G11C7/1084 ,  G11C29/025 ,  G11C29/028 ,  G11C2207/105

Abstract: Apparatuses and methods are disclosed herein, including those, performed by a memory die, that operate to detect that a command on a bus connected to the memory die is addressed to another memory die responsive to a chip select signal, and to change the impedance of an on-die termination circuit of the memory die responsive to the detecting.

Abstract translation: 本文公开的装置和方法包括由存储管芯执行的装置和方法，其操作用于检测连接到存储管芯的总线上的命令是否响应于芯片选择信号寻址到另一存储器管芯，并且改变阻抗 存储器管芯的片上终端电路响应于检测。

公开(公告)号：US20150098285A1

公开(公告)日：2015-04-09

申请号：US14045521

申请日：2013-10-03

Applicant: Micron Technology, Inc.

Inventor： Brian W. Huber ,  Vijay Vankayala ,  Brian Gross ,  Gary Howe ,  Roy E. Greeff

IPC: G11C7/02

CPC classification number: G11C7/02 ,  G11C5/063 ,  G11C7/1057 ,  G11C7/1084 ,  G11C29/025 ,  G11C29/028 ,  G11C2207/105

Abstract: Apparatuses and methods are disclosed herein, including those, performed by a memory die, that operate to detect that a command on a bus connected to the memory die is addressed to another memory die responsive to a chip select signal, and to change the impedance of an on-die termination circuit of the memory die responsive to the detecting.

Abstract translation: 本文公开的装置和方法包括由存储管芯执行的装置和方法，其操作用于检测连接到存储管芯的总线上的命令是否响应于芯片选择信号寻址到另一存储器管芯，并且改变阻抗 存储器管芯的片上终端电路响应于检测。