公开(公告)号：US12046293B2

公开(公告)日：2024-07-23

申请号：US17820906

申请日：2022-08-19

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chun-Chang Lu ,  Wen-Jer Tsai ,  Wei-Liang Lin

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/24 ,  G11C16/34

CPC classification number: G11C16/16 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/24 ,  G11C16/344

Abstract: A memory device and a method for operating selective erase scheme are provided. In an erase operation, a switch voltage is applied to at least one of a string select line or a ground select line of a selected sub-block of a selected block, a gate control voltage is applied to selected word lines of the selected sub-block, and an erase voltage is applied to bit lines and a common source line of the selected sub-block. The switch voltage is smaller than the erase voltage. The gate control voltage is smaller than the switch voltage and the erase voltage.

公开(公告)号：US11641744B2

公开(公告)日：2023-05-02

申请号：US17670570

申请日：2022-02-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Liang Lin ,  Wen-Jer Tsai

IPC: H10B43/27 ,  H01L21/762 ,  H01L29/423 ,  H01L21/02 ,  H01L21/311 ,  H01L21/28 ,  H01L29/788 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/04 ,  H01L21/3205 ,  H01L21/3213

Abstract: A memory device and a method for fabricating the memory device are provided. The memory device includes a substrate having an upper surface; a stacked structure disposed on the upper surface of the substrate, wherein the stacked structure includes a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer and a third insulating layer sequentially stacked on the substrate; a plurality of channel structures penetrating the stacked structure and electrically connected to the substrate, wherein each of the channel structures includes an upper portion corresponding to the second conductive layer and a lower portion corresponding to the first conductive layer; a memory layer disposed between the second conductive layer and the upper portion; and a plurality of isolation structures penetrating the stacked structure to separate the stacked structure into a plurality of sub-stacks.

公开(公告)号：US10460797B2

公开(公告)日：2019-10-29

申请号：US15698812

申请日：2017-09-08

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shaw-Hung Ku ,  Ta-Wei Lin ,  Cheng-Hsien Cheng ,  Chih-Wei Lee ,  Wen-Jer Tsai

IPC: G11C16/04 ,  G11C11/56 ,  G11C16/34

Abstract: A method for programming a non-volatile memory and a memory system are provided. Each of multiple cells of the non-volatile memory stores data having at least 2 bits. The method includes the following steps. At least one programming pulse is provided for programming a target cell of the cells. At least one program-verify pulse is provided for verifying whether the target cell is successfully programmed. It is determined that whether a threshold voltage of the target cell is greater than or equal to a program-verify voltage. When the threshold voltage is greater than or equal to the program-verify voltage, the target cell is set as successfully programmed. Next, a post-verifying operation is performed to the successfully programmed cell. The post-verifying operation includes determining whether the threshold voltage of the target cell is greater than or equal to a post-verifying voltage.

公开(公告)号：US09070588B2

公开(公告)日：2015-06-30

申请号：US14459050

申请日：2014-08-13

Applicant: MACRONIX International Co., Ltd.

Inventor： Chih-Chieh Cheng ,  Shih-Guei Yan ,  Wen-Jer Tsai

IPC: H01L29/792 ,  H01L27/115 ,  H01L29/66 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L27/11563 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

Abstract: A non-volatile memory structure, including a substrate, a plurality of stacked structures, a plurality of first conductive type doped regions, at least one second conductive type doped region, a conductive layer, and a first dielectric layer, is provided. The stacked structures are disposed on the substrate, and each of the stacked structures includes a charge storage structure. The first conductive type doped regions are disposed in the substrate under the corresponding charge storage structures respectively. The second conductive type doped region is disposed in the substrate between the adjacent charge storage structures and has an overlap region with each of the charge storage structures. The conductive layer covers the second conductive type doped region. The first dielectric layer is disposed between the conductive layer and the second conductive type doped region.

Abstract translation: 提供了包括基板，多个堆叠结构，多个第一导电型掺杂区域，至少一个第二导电型掺杂区域，导电层和第一介电层的非易失性存储器结构。 堆叠结构设置在基板上，并且每个堆叠结构都包括电荷存储结构。 第一导电型掺杂区域分别设置在相应的电荷存储结构下的衬底中。 第二导电型掺杂区域设置在相邻的电荷存储结构之间的衬底中，并且与每个电荷存储结构具有重叠区域。 导电层覆盖第二导电型掺杂区域。 第一介电层设置在导电层和第二导电型掺杂区之间。

公开(公告)号：US20140239370A1

公开(公告)日：2014-08-28

申请号：US13774449

申请日：2013-02-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Guei Yan ,  Wen-Jer Tsai ,  Ping-Hung Tsai

IPC: H01L29/792 ,  H01L29/66

CPC classification number: H01L29/66833 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/66825 ,  H01L29/7887 ,  H01L29/7923

Abstract: Provided is a memory device including a first dielectric layer, a T-shaped gate, two charge storage layers and two second dielectric layers. The first dielectric layer is disposed on a substrate. The T-shaped gate is disposed on the first dielectric layer and has an upper gate and a lower gate, wherein two gaps are present respectively at both sides of the lower gate and between the upper gate and the substrate. The charge storage layers are respectively embedded into the gaps. A second dielectric layer is disposed between each charge storage layer and the upper gate, between each charge storage layer and the lower gate and between each charge storage layer and the substrate.

Abstract translation: 提供了包括第一介电层，T形栅极，两个电荷存储层和两个第二电介质层的存储器件。 第一电介质层设置在基板上。 T形栅极设置在第一介电层上并具有上栅极和下栅极，其中两个间隙分别存在于下栅极的两侧以及上栅极和衬底之间。 电荷存储层分别嵌入到间隙中。 在每个电荷存储层和上部栅极之间，在每个电荷存储层和下部栅极之间以及每个电荷存储层和衬底之间设置第二介电层。