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公开(公告)号：US09048136B2
公开(公告)日：2015-06-02
申请号：US13282261
申请日：2011-10-26
申请人： Randy W. Mann , Scott D. Luning
发明人： Randy W. Mann , Scott D. Luning
IPC分类号： G11C11/00 , H01L27/11 , H01L27/12 , G11C11/412 , G11C11/419
CPC分类号： H01L27/1108 , G11C11/412 , G11C11/419 , H01L27/1203
摘要： A static random access memory cell is provided formed in a silicon layer over a buried oxide layer on a substrate and including first and second inverters each having a pull-up and pull-down transistor configured to form a cell node. Each of the pull-down transistors of the first and second inverters are formed over first regions below the buried oxide layer with the first regions having a first doping level forming first backgates for the pull-down transistors. A pair of passgate transistors respectively couples to the cell nodes of the first and second inverters and each are formed over second regions below the buried oxide layer with the second regions having a second doping level forming second backgates for the passgate transistors. Active bias circuitry applies potentials to the first and second backgates during read, standby and write operations of the static random access memory cell.
摘要翻译： 提供了在衬底上的掩埋氧化物层上的硅层中形成的静态随机存取存储器单元，并且包括第一和第二反相器，每个具有被配置为形成单元节点的上拉和下拉晶体管。 第一和第二反相器的每个下拉晶体管形成在掩埋氧化物层下方的第一区域上，其中第一区域具有形成用于下拉晶体管的第一衬底的第一掺杂级。 一对通道晶体管分别耦合到第一和第二反相器的单元节点，并且每一个均形成在掩埋氧化物层下方的第二区域上，其中第二区域具有形成用于通路晶体管的第二衬底的第二掺杂水平。 主动偏置电路在静态随机存取存储器单元的读取，备用和写入操作期间将电位施加到第一和第二后挡板。
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公开(公告)号：US20130107610A1
公开(公告)日：2013-05-02
申请号：US13282299
申请日：2011-10-26
申请人： Randy W. Mann , Scott D. Luning
发明人： Randy W. Mann , Scott D. Luning
IPC分类号： G11C11/34 , H01L21/8238 , G11C11/00
CPC分类号： H01L27/0207 , G11C11/412 , H01L27/1104 , Y10S257/903
摘要： A static random access memory cell is provided that includes first and second inverters formed on a substrate each having a pull-up and pull-down transistor configured to form a cell node. Each of the pull-down transistors of the first and second inverters resides over first regions below the buried oxide layer and having a first doping level and applied bias providing a first voltage threshold for the pull-down transistors. A pair of passgate transistors is coupled the cell nodes of the first and second inverters, and each is formed over second regions below the buried oxide layer and having a second doping level and applied bias providing a second voltage threshold for the passgate transistors. The first voltage threshold differs from the second voltage threshold providing electrical voltage threshold control between the pull-down transistors and the passgate transistors.
摘要翻译： 提供了一种静态随机存取存储单元，其包括形成在基板上的第一和第二反相器，每个具有被配置为形成单元节点的上拉和下拉晶体管。 第一和第二反相器的每个下拉晶体管驻留在掩埋氧化物层下方的第一区域上，并且具有第一掺杂水平和施加的偏压，为下拉晶体管提供第一电压阈值。 一对通道晶体管耦合第一和第二反相器的单元节点，并且每一个形成在掩埋氧化物层下方的第二区域上，并且具有第二掺杂水平，并且施加的偏置为通路晶体管提供第二电压阈值。 第一电压阈值与提供下拉晶体管和通道晶体管之间的电压阈值控制的第二电压阈值不同。
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公开(公告)号：US20130107608A1
公开(公告)日：2013-05-02
申请号：US13282261
申请日：2011-10-26
申请人： Randy W. Mann , Scott D. Luning
发明人： Randy W. Mann , Scott D. Luning
CPC分类号： H01L27/1108 , G11C11/412 , G11C11/419 , H01L27/1203
摘要： A static random access memory cell is provided formed in a silicon layer over a buried oxide layer on a substrate and including first and second inverters each having a pull-up and pull-down transistor configured to form a cell node. Each of the pull-down transistors of the first and second inverters are formed over first regions below the buried oxide layer with the first regions having a first doping level forming first backgates for the pull-down transistors. A pair of passgate transistors respectively couples to the cell nodes of the first and second inverters and each are formed over second regions below the buried oxide layer with the second regions having a second doping level forming second backgates for the passgate transistors. Active bias circuitry applies potentials to the first and second backgates during read, standby and write operations of the static random access memory cell.
摘要翻译： 提供了在衬底上的掩埋氧化物层上的硅层中形成的静态随机存取存储器单元，并且包括第一和第二反相器，每个具有被配置为形成单元节点的上拉和下拉晶体管。 第一和第二反相器的每个下拉晶体管形成在掩埋氧化物层下方的第一区域上，其中第一区域具有形成用于下拉晶体管的第一衬底的第一掺杂级。 一对通道晶体管分别耦合到第一和第二反相器的单元节点，并且每一个均形成在掩埋氧化物层下方的第二区域上，其中第二区域具有形成用于通路晶体管的第二衬底的第二掺杂水平。 主动偏置电路在静态随机存取存储器单元的读取，备用和写入操作期间将电位施加到第一和第二后挡板。
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公开(公告)号：US08099688B2
公开(公告)日：2012-01-17
申请号：US11985961
申请日：2007-11-19
申请人： Wayne F. Ellis , Randy W. Mann , David J. Wager , Robert C. Wong
发明人： Wayne F. Ellis , Randy W. Mann , David J. Wager , Robert C. Wong
IPC分类号： G06F17/50
CPC分类号： G11C11/413 , G11C5/14
摘要： A design process includes inputting a design file representing a circuit design embodied in a non-transitory computer-readable medium, and using a computer to translate the circuit design into a netlist. The netlist comprises a representation of a plurality of wires, transistors, and logic gates, and is stored in the non-transitory computer-readable medium. When executed by the computer, the netlist produces the circuit design. The circuit design comprises a static random access memory (“SRAM”) including a plurality of SRAM cells arranged in an array, including a plurality of rows and a plurality of columns, and a plurality of column voltage control circuits corresponding to respective ones of the plurality of columns of the array. Each of the plurality of voltage control circuits is coupled to an output of a power supply and is operable to temporarily reduce a voltage upon arrival of a bit select signal provided to power supply inputs of a plurality of SRAM cells belonging to a selected column of the plurality of columns. The selected column is selected during a write operation in which a bit is written to one of the plurality of SRAM cells belonging to the selected column. Each column voltage control circuit includes an NFET and a pair of PFETs. Each NFET and pair of PFETs has a conduction path directly connected between the output of the power supply and the power supply inputs of the plurality of SRAM cells.
摘要翻译： 设计过程包括输入表示在非暂时计算机可读介质中体现的电路设计的设计文件，并使用计算机将电路设计转换成网表。 网表包括多个线，晶体管和逻辑门的表示，并且存储在非暂时计算机可读介质中。 当由计算机执行时，网表产生电路设计。 该电路设计包括一个静态随机存取存储器（“SRAM”），它包括多个排列成阵列的SRAM单元，包括多行和多列，以及多个列电压控制电路， 阵列的多列。 多个电压控制电路中的每一个耦合到电源的输出，并且可操作以在到达时临时减小提供给属于所选择的列的所选列的多个SRAM单元的电源输入的位选择信号 多列。 在写入操作期间选择所选列，其中将位写入属于所选列的多个SRAM单元之一。 每列电压控制电路包括NFET和一对PFET。 每个NFET和一对PFET具有直接连接在电源的输出端与多个SRAM单元的电源输入端之间的导通路径。
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公开(公告)号：US20090200642A1
公开(公告)日：2009-08-13
申请号：US12028145
申请日：2008-02-08
IPC分类号： H01L29/93
CPC分类号： H01L29/93
摘要： An array of deep trenches is formed in a doped portion of the semiconductor substrate, which forms a lower electrode. A dielectric layer is formed on the sidewalls of the array of deep trenches. The array of deep trenches is filled with a doped semiconductor material to form an upper electrode comprising a top plate portion and a plurality of extension portions into the array of trenches. In a depletion mode, the bias condition across the dielectric layer depletes majority carriers within the top electrode, thus providing a low capacitance. In an accumulation mode, the bias condition attracts majority carriers toward the dielectric layer, providing a high capacitance. Thus, the trench metal-oxide-semiconductor (MOS) varactor provides a variable capacitance depending on the polarity of the bias.
摘要翻译： 在半导体衬底的掺杂部分中形成深沟槽阵列，形成下电极。 在深沟槽阵列的侧壁上形成介电层。 深沟槽阵列用掺杂半导体材料填充以形成上电极，其包括顶板部分和多个延伸部分到沟槽阵列中。 在耗尽模式中，跨越电介质层的偏置条件消耗顶部电极内的多数载流子，从而提供低电容。 在累积模式中，偏置条件吸引多数载流子朝向电介质层，提供高电容。 因此，沟槽金属氧化物半导体（MOS）变容二极管根据偏压的极性提供可变电容。
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公开(公告)号：US20090129191A1
公开(公告)日：2009-05-21
申请号：US11985961
申请日：2007-11-19
申请人： Wayne F. Ellis , Randy W. Mann , David J. Wager , Robert C. Wong
发明人： Wayne F. Ellis , Randy W. Mann , David J. Wager , Robert C. Wong
IPC分类号： G11C5/14
CPC分类号： G11C11/413 , G11C5/14
摘要： A design structure including a static random access memory (“SRAM”) is provided which includes a plurality of SRAM cells arranged in an array. The array includes a plurality of rows and a plurality of columns. The SRAM includes voltage control circuits corresponding to respective ones of the plurality of columns of the array, each coupled to an output of a power supply. Each voltage control circuit temporarily reduces a voltage provided to power supply inputs of a plurality of SRAM cells that belong to a selected column of columns of the SRAM. The power supply voltage to the selected column is reduced during a write operation in which a bit is written to one of the SRAM cells belonging to the selected column.
摘要翻译： 提供了包括静态随机存取存储器（“SRAM”）的设计结构，其包括以阵列布置的多个SRAM单元。 阵列包括多个行和多个列。 SRAM包括对应于阵列的多个列中的相应列的电压控制电路，每个耦合到电源的输出端。 每个电压控制电路暂时降低提供给属于SRAM的选定列列的多个SRAM单元的电源输入的电压。 在将位写入属于所选列的SRAM单元之一的写操作期间，对所选列的电源电压降低。
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公开(公告)号：US20080268604A1
公开(公告)日：2008-10-30
申请号：US12128077
申请日：2008-05-28
申请人： Peter J. Geiss , Marwan H. Khater , Qizhi Liu , Randy W. Mann , Robert J. Purtell , BethAnn Rainey , Jae-Sung Rieh , Andreas D. Stricker
发明人： Peter J. Geiss , Marwan H. Khater , Qizhi Liu , Randy W. Mann , Robert J. Purtell , BethAnn Rainey , Jae-Sung Rieh , Andreas D. Stricker
IPC分类号： H01L21/331
CPC分类号： H01L29/66242 , H01L21/28518 , H01L21/8249 , H01L27/0623 , H01L29/0804 , H01L29/456 , H01L29/7371
摘要： Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.
摘要翻译： 提供了制造具有凸起非本征基极的异质结双极晶体管的方法，其中通过在以自对准方式延伸到发射极区域的凸起的外部基极之上形成硅化物来降低基极电阻。 在形成凸起的外基之后，将硅化物形成结合到BiCMOS工艺流程中。 本发明还提供了一种异质结双极晶体管，其具有凸起的外部基极和位于凸起外部基极顶部的硅化物。 凸起的外基极上面的硅化物以自对准的方式延伸到发射极。 发射极通过间隔物与硅化物分离。
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公开(公告)号：US06962838B2
公开(公告)日：2005-11-08
申请号：US10447579
申请日：2003-05-29
CPC分类号： H01L29/7842 , H01L21/84 , H01L27/1203
摘要： The present invention provides a device design and method for forming Field Effect Transistors (FETs) that have improved performance without negative impacts to device density. The present invention forms high-gain p-channel transistors by forming them on silicon islands where hole mobility has been increased. The hole mobility is increased by applying physical straining to the silicon islands. By straining the silicon islands, the hole mobility is increased resulting in increased device gain. This is accomplished without requiring an increase in the size of the devices, or the size of the contacts to the devices.
摘要翻译： 本发明提供了一种用于形成场效应晶体管（FET）的器件设计和方法，其具有改进的性能而不会对器件密度造成负面影响。 本发明通过在硅岛上形成高增益p沟道晶体管，其中空穴迁移率已经增加。 通过对硅岛施加物理应变来增加空穴迁移率。 通过拉伸硅岛，空穴迁移率增加，导致器件增益增加。 这是在不需要增加设备尺寸或者与设备的触点的尺寸的情况下实现的。
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公开(公告)号：US06946376B2
公开(公告)日：2005-09-20
申请号：US10173950
申请日：2002-06-17
IPC分类号： H01L21/28 , H01L21/336 , H01L21/60 , H01L21/768 , H01L23/485 , H01L23/522 , H01L29/78
CPC分类号： H01L21/76897 , H01L21/76838 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A method of forming conductive contacts to drain and source regions of a semiconductor device such as a field effect transistor (FET). A gate structure is formed over a portion of a semiconductor substrate, wherein the gate structure includes: a gate dielectric on a surface of the semiconductor substrate, a conductive gate aligned on the gate dielectric, a silicide layer aligned on the conductive gate, and a silicon nitride cap aligned on the silicide layer. Insulative spacers are formed on sidewalls of the gate structure, and the insulative spacers contact the semiconductor substrate. A drain region and a source region are formed within the semiconductor substrate, wherein a channel region is disposed between the drain region and the source region, and wherein the gate structure is over the channel region. After an insulative region containing a photosensitive material, such as boro-phoso-silicate glass, is formed over the gate structure and the semiconductor substrate, a cavity over the drain region and a cavity over the source region are formed photolithographically. The cavities are filled with conductive material such as tungsten, forming a conductive contact to the drain region and a conductive contact to the source region. The top surfaces of the conductive contacts and the top surface of the gate structure are coplanar.
摘要翻译： 在诸如场效应晶体管（FET）的半导体器件的漏极和源极区域中形成导电接触的方法。 栅极结构形成在半导体衬底的一部分上，其中栅极结构包括：在半导体衬底的表面上的栅极电介质，在栅极电介质上对准的导电栅极，在导电栅极上对准的硅化物层，以及 在硅化物层上对准氮化硅盖。 绝缘垫片形成在栅极结构的侧壁上，并且绝缘垫片与半导体衬底接触。 漏极区域和源极区域形成在半导体衬底内，其中沟道区域设置在漏极区域和源极区域之间，并且其中栅极结构在沟道区域之上。 在栅极结构和半导体衬底之上形成含有光敏材料（例如硼硅酸盐玻璃）的绝缘区域之后，光刻地形成在漏极区域上方的空腔和源极区域上的空腔。 空穴填充有诸如钨的导电材料，形成与漏极区域的导电接触以及与源极区域的导电接触。 导电触点的顶表面和栅极结构的顶表面是共面的。
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公开(公告)号：US06445050B1
公开(公告)日：2002-09-03
申请号：US09500361
申请日：2000-02-08
IPC分类号： H01L2972
CPC分类号： H01L21/76897 , H01L21/76838 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A method of forming conductive contacts to drain and source regions of a semiconductor device such as a field effect transistor (FET). A gate structure is formed over a portion of a semiconductor substrate, wherein the gate structure includes: a gate dielectric on a surface of the semiconductor substrate, a conductive gate aligned on the gate dielectric, a silicide layer aligned on the conductive gate, and a silicon nitride cap aligned on the silicide layer. Insulative spacers are formed on sidewalls of the gate structure, and the insulative spacers contact the semiconductor substrate. A drain region and a source region are formed within the semiconductor substrate, wherein a channel region is disposed between the drain region and the source region, and wherein the gate structure is over the channel region. After an insulative region containing a photosensitive material, such as boro-phoso-silicate glass, is formed over the gate structure and the semiconductor substrate, a cavity over the drain region and a cavity over the source region are formed photolithographically. The cavities are filled with conductive material such as tungsten, forming a conductive contact to the drain region and a conductive contact to the source region. The top surfaces of the conductive contacts and the top surface of the gate structure are coplanar.
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