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公开(公告)号：US06946376B2
公开(公告)日：2005-09-20
申请号：US10173950
申请日：2002-06-17
IPC分类号： H01L21/28 , H01L21/336 , H01L21/60 , H01L21/768 , H01L23/485 , H01L23/522 , H01L29/78
CPC分类号： H01L21/76897 , H01L21/76838 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A method of forming conductive contacts to drain and source regions of a semiconductor device such as a field effect transistor (FET). A gate structure is formed over a portion of a semiconductor substrate, wherein the gate structure includes: a gate dielectric on a surface of the semiconductor substrate, a conductive gate aligned on the gate dielectric, a silicide layer aligned on the conductive gate, and a silicon nitride cap aligned on the silicide layer. Insulative spacers are formed on sidewalls of the gate structure, and the insulative spacers contact the semiconductor substrate. A drain region and a source region are formed within the semiconductor substrate, wherein a channel region is disposed between the drain region and the source region, and wherein the gate structure is over the channel region. After an insulative region containing a photosensitive material, such as boro-phoso-silicate glass, is formed over the gate structure and the semiconductor substrate, a cavity over the drain region and a cavity over the source region are formed photolithographically. The cavities are filled with conductive material such as tungsten, forming a conductive contact to the drain region and a conductive contact to the source region. The top surfaces of the conductive contacts and the top surface of the gate structure are coplanar.
摘要翻译： 在诸如场效应晶体管（FET）的半导体器件的漏极和源极区域中形成导电接触的方法。 栅极结构形成在半导体衬底的一部分上，其中栅极结构包括：在半导体衬底的表面上的栅极电介质，在栅极电介质上对准的导电栅极，在导电栅极上对准的硅化物层，以及 在硅化物层上对准氮化硅盖。 绝缘垫片形成在栅极结构的侧壁上，并且绝缘垫片与半导体衬底接触。 漏极区域和源极区域形成在半导体衬底内，其中沟道区域设置在漏极区域和源极区域之间，并且其中栅极结构在沟道区域之上。 在栅极结构和半导体衬底之上形成含有光敏材料（例如硼硅酸盐玻璃）的绝缘区域之后，光刻地形成在漏极区域上方的空腔和源极区域上的空腔。 空穴填充有诸如钨的导电材料，形成与漏极区域的导电接触以及与源极区域的导电接触。 导电触点的顶表面和栅极结构的顶表面是共面的。
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公开(公告)号：US06445050B1
公开(公告)日：2002-09-03
申请号：US09500361
申请日：2000-02-08
IPC分类号： H01L2972
CPC分类号： H01L21/76897 , H01L21/76838 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A method of forming conductive contacts to drain and source regions of a semiconductor device such as a field effect transistor (FET). A gate structure is formed over a portion of a semiconductor substrate, wherein the gate structure includes: a gate dielectric on a surface of the semiconductor substrate, a conductive gate aligned on the gate dielectric, a silicide layer aligned on the conductive gate, and a silicon nitride cap aligned on the silicide layer. Insulative spacers are formed on sidewalls of the gate structure, and the insulative spacers contact the semiconductor substrate. A drain region and a source region are formed within the semiconductor substrate, wherein a channel region is disposed between the drain region and the source region, and wherein the gate structure is over the channel region. After an insulative region containing a photosensitive material, such as boro-phoso-silicate glass, is formed over the gate structure and the semiconductor substrate, a cavity over the drain region and a cavity over the source region are formed photolithographically. The cavities are filled with conductive material such as tungsten, forming a conductive contact to the drain region and a conductive contact to the source region. The top surfaces of the conductive contacts and the top surface of the gate structure are coplanar.
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3.发明授权公开(公告)号：US08299537B2
公开(公告)日：2012-10-30
申请号：US12369099
申请日：2009-02-11
申请人： Joseph R. Greco , Kevin Munger , Richard A. Phelps , Jennifer C. Robbins , William Savaria , James A. Slinkman , Randy L. Wolf
发明人： Joseph R. Greco , Kevin Munger , Richard A. Phelps , Jennifer C. Robbins , William Savaria , James A. Slinkman , Randy L. Wolf
IPC分类号： H01L21/70
CPC分类号： H01L21/7624 , H01L21/26506 , H01L21/84 , H01L27/1203
摘要： A semiconductor-on-insulator substrate and a related semiconductor structure, as well as a method for fabricating the semiconductor-on-insulator substrate and the related semiconductor structure, provide for a multiple order radio frequency harmonic suppressing region located and formed within a base semiconductor substrate at a location beneath an interface of a buried dielectric layer with the base semiconductor substrate within the semiconductor-on-insulator substrate. The multiple order radio frequency harmonic suppressing region may comprise an ion implanted atom, such as but not limited to a noble gas atom, to provide a suppressed multiple order radio frequency harmonic when powering a radio frequency device, such as but not limited to a radio frequency complementary metal oxide semiconductor device (or alternatively a passive device), located and formed within and upon a surface semiconductor layer within the semiconductor structure.
摘要翻译： 绝缘体上半导体衬底和相关半导体结构以及绝缘体上半导体衬底和相关半导体结构的制造方法提供了一种位于并形成在基底半导体内的多阶射频谐波抑制区域 在绝缘体上半导体衬底内的掩埋介质层与基底半导体衬底的界面下方的位置处的衬底。 多级射频谐波抑制区域可以包括离子注入原子，例如但不限于稀有气体原子，以在对射频设备供电时提供抑制的多阶射频谐波，例如但不限于无线电 位于和形成在半导体结构内的表面半导体层内和之上的高频互补金属氧化物半导体器件（或替代地，无源器件）。
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4.发明申请LATERAL EXTENDED DRAIN METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (LEDMOSFET) HAVING A HIGH DRAIN-TO-BODY BREAKDOWN VOLTAGE (Vb), A METHOD OF FORMING AN LEDMOSFET, AND A SILICON-CONTROLLED RECTIFIER (SCR) INCORPORATING A COMPLEMENTARY PAIR OF LEDMOSFETS 有权具有高排水 - 体积断电电压（Vb），形成LEDMOSFET的方法，以及包含LEDMOSFETS的补充对的硅控制整流器（SCR）的侧向延伸漏极金属氧化物半导体场效应晶体管（LEDMOSFET）公开(公告)号：US20120168817A1
公开(公告)日：2012-07-05
申请号：US13238414
申请日：2011-09-21
申请人： Michel J. Abou-Khalil , Alan B. Botula , Alvin J. Joseph , Theodore J. Letavic , James A. Slinkman
发明人： Michel J. Abou-Khalil , Alan B. Botula , Alvin J. Joseph , Theodore J. Letavic , James A. Slinkman
IPC分类号： H01L27/088 , H01L21/76 , H01L21/336 , H01L29/78
CPC分类号： H01L29/66681 , H01L29/402 , H01L29/407 , H01L29/4238 , H01L29/66704 , H01L29/66795 , H01L29/7436 , H01L29/7824 , H01L29/7825 , H01L29/785
摘要： Disclosed are embodiments of a lateral, extended drain, metal oxide semiconductor, field effect transistor (LEDMOSFET) having a high drain-to-body breakdown voltage. Discrete conductive field (CF) plates are adjacent to opposing sides of the drain drift region, each having an angled sidewall such that the area between the drain drift region and the CF plate has a continuously increasing width along the length of the drain drift region from the channel region to the drain region. The CF plates can comprise polysilicon or metal structures or dopant implant regions within the same semiconductor body as the drain drift region. The areas between the CF plates and the drain drift region can comprise tapered dielectric regions or, alternatively, tapered depletion regions within the same semiconductor body as the drain drift region. Also disclosed are embodiments of a method for forming an LEDMOSFET and embodiments of a silicon-controlled rectifier (SCR) incorporating such LEDMOSFETs.
摘要翻译： 公开了具有高漏极对体击穿电压的横向延伸漏极，金属氧化物半导体，场效应晶体管（LEDMOSFET）的实施例。 离散导电场（CF）板与漏极漂移区的相对侧相邻，每侧具有成角度的侧壁，使得漏极漂移区和CF板之间的区域沿着漏极漂移区的长度具有连续增加的宽度， 沟道区到漏极区。 CF板可以包括与漏极漂移区相同的半导体主体内的多晶硅或金属结构或掺杂剂注入区。 CF板和漏极漂移区域之间的区域可以包括与漏极漂移区域相同的半导体本体内的锥形介质区域或者替代地，锥形耗尽区域。 还公开了用于形成LEDMOSFET的方法的实施例和结合了这种LEDMOSFET的可控硅整流器（SCR）的实施例。
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5.发明申请SILICON-ON-INSULATOR (SOI) STRUCTURE CONFIGURED FOR REDUCED HARMONICS AND METHOD OF FORMING THE STRUCTURE 有权用于减少谐波的硅绝缘体（SOI）结构和形成结构的方法公开(公告)号：US20110127529A1
公开(公告)日：2011-06-02
申请号：US12627343
申请日：2009-11-30
申请人： Alan B. Botula , John J. Ellis-Monaghan , Alvin J. Joseph , Max G. Levy , Richard A. Phelps , James A. Slinkman , Randy L. Wolf
发明人： Alan B. Botula , John J. Ellis-Monaghan , Alvin J. Joseph , Max G. Levy , Richard A. Phelps , James A. Slinkman , Randy L. Wolf
IPC分类号： H01L27/12 , H01L21/762
CPC分类号： H01L21/02488 , H01L21/2652 , H01L21/7624 , H01L21/84 , H01L27/1203 , H01L29/78603
摘要： Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure.
摘要翻译： 公开了在半导体衬底上具有绝缘体层并且器件层位于绝缘体层上的半导体结构。 衬底掺杂有相对低剂量的具有给定导电类型的掺杂剂，使得其具有相对高的电阻率。 此外，与绝缘体层紧密相邻的半导体衬底的一部分可掺杂略高的相同掺杂剂剂量，具有相同导电类型的不同掺杂剂或其组合。 可选地，在该相同部分内形成微腔，以便平衡由于掺杂增加导致的电导率的增加，同时具有相应的电阻率增加。 增加半导体衬底 - 绝缘体层界面处的掺杂剂浓度会提高任何结果的寄生电容器的阈值电压（Vt），从而降低谐波行为。 本文还公开了用于形成这种半导体结构的方法的实施例。
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公开(公告)号：US07585614B2
公开(公告)日：2009-09-08
申请号：US10711458
申请日：2004-09-20
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Peter H. Mitchell , Larry A. Nesbit , James A. Slinkman
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Peter H. Mitchell , Larry A. Nesbit , James A. Slinkman
IPC分类号： G03F7/00
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/0338 , H01L21/32139
摘要： A method of patterning which provides images substantially smaller than that possible by lithographic techniques is provided. In the method of the invention, a substrate has a memory layer and a sacrificial layer formed thereon. An image is patterned onto the memory layer by protecting an edge during an etching step using chemical oxide removal (COR) processes, for example. Another edge is memorized in the layer. The sacrificial layer is removed to expose another memorized edge, which is used to define a pattern in an underlying layer.
摘要翻译： 提供了一种通过光刻技术提供显着小于可能的图像的图案化方法。 在本发明的方法中，衬底具有形成在其上的存储层和牺牲层。 例如，通过使用化学氧化物去除（COR）工艺在蚀刻步骤期间保护边缘，将图像图案化到存储层上。 另一个边缘被记住在图层中。 去除牺牲层以露出另一个存储的边缘，其用于在下层中定义图案。
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7.发明申请SYSTEM AND METHOD FOR DETECTING LOCAL MECHANICAL STRESS IN INTEGREATED DEVICES 有权用于检测集成设备中的局部机械应力的系统和方法公开(公告)号：US20090219508A1
公开(公告)日：2009-09-03
申请号：US12039830
申请日：2008-02-29
IPC分类号： G01B11/16
摘要： A method of detecting local mechanical stress in integrated devices is provided, the method comprising: enabling the detection of a photovoltage difference between a scan probe device and a surface portion of an integrated device, the scan probe device being configured to deflect in response to the photovoltage difference; measuring the deflection of the scan probe device in response to the photovoltage difference between the scan probe device and the surface portion of the integrated device; and calculating a local stress level within the integrated device by determining a local work function of the surface portion of the integrated device based upon the deflection of the scan probe device.
摘要翻译： 提供了一种在集成器件中检测局部机械应力的方法，所述方法包括：使得能够检测扫描探针器件与集成器件的表面部分之间的光电压差，扫描探针器件被配置为响应于 光电压差; 测量所述扫描探针装置响应于所述扫描探针装置与所述集成装置的所述表面部分之间的光电压差的偏转; 以及通过基于所述扫描探针装置的偏转来确定所述集成装置的所述表面部分的局部功函数来计算所述集成装置内的局部应力水平。
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公开(公告)号：US20090110898A1
公开(公告)日：2009-04-30
申请号：US11931371
申请日：2007-10-31
申请人： Max Levy , Dale Martin , Gerd Pfeiffer , James A. Slinkman
发明人： Max Levy , Dale Martin , Gerd Pfeiffer , James A. Slinkman
CPC分类号： H01L21/76254 , H01L21/76256 , H01L29/78603 , Y10T428/249921 , Y10T428/31504
摘要： A method of forming a semiconductor-on-insulator (SOI) substrate using a thermal annealing process to provide a semiconductor base wafer having a thin high resistivity surface layer that is positioned at the interface with the buried insulating layer is provided. Specifically, the inventive method fabricates an a semiconductor-on-insulator (SOI) substrate having an SOI layer and a semiconductor base wafer that are separated, at least in part, by a buried insulating layer, wherein the semiconductor base wafer includes a high resistivity (HR) surface layer located on a lower resistivity semiconductor portion of the semiconductor base wafer, and the HR surface layer forms an interface with the buried insulating layer.
摘要翻译： 提供一种使用热退火工艺形成绝缘体上半导体（SOI）衬底的方法，以提供具有位于与掩埋绝缘层的界面处的薄的高电阻率表面层的半导体基底晶片。 具体地，本发明的方法制造具有至少部分由掩埋绝缘层分离的SOI层和半导体基底晶片的绝缘体上半导体（SOI）衬底，其中半导体基底晶片包括高电阻率 （HR）表层，并且所述HR表面层与所述掩埋绝缘层形成界面。
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9.发明授权Method for adjusting lithographic mask flatness using thermally induced pellicle stress 有权使用热诱导防护薄膜应力调整光刻胶片平整度的方法公开(公告)号：US07355680B2
公开(公告)日：2008-04-08
申请号：US10905453
申请日：2005-01-05
摘要： A method for adjusting the flatness of a lithographic mask includes determining an initial mask flatness of the mask, determining an applied stress for bringing the mask to a desired mask flatness, and determining a mounting temperature of a pellicle frame to be mounted to the mask, the mounting temperature corresponding to the applied stress. The actual temperature of the pellicle frame is adjusted to the determined mounting temperature.
摘要翻译： 调整光刻掩模的平坦度的方法包括：确定掩模的初始掩模平坦度，确定施加的应力以使掩模达到期望的掩模平坦度，以及确定要安装到掩模的防护薄膜组件框架的安装温度， 安装温度对应于施加的应力。 将防护膜框架的实际温度调整到确定的安装温度。
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10.发明授权STI stress modification by nitrogen plasma treatment for improving performance in small width devices 失效通过氮等离子体处理进行STI应力改进，以改善小宽度器件的性能公开(公告)号：US06887798B2
公开(公告)日：2005-05-03
申请号：US10250047
申请日：2003-05-30
IPC分类号： H01L21/318 , H01L21/762 , H01L29/10 , H01L21/31 , H01L21/469
CPC分类号： H01L29/7842 , H01L21/3185 , H01L21/76237 , H01L29/1033
摘要： A method for modulating the stress caused by bird beak formation of small width devices by a nitrogen plasma treatment. The nitrogen plasma process forms a nitride liner about the trench walls that serves to prevent the formation of bird beaks in the isolation region during a subsequent oxidation step. In one embodiment, the plasma nitridation process occurs after trench etching, but prior to trench fill. In yet another embodiment, the plasma nitridation process occurs after trench fill. In yet another embodiment, a block mask is formed over predetermined active areas of the etched substrate prior to the plasma nitridation process. This embodiment is used in protecting the PFET device area from the plasma nitridation process thereby providing a means to form a PFET device area in which stress caused by bird beak formation increases the device performance of the PFET.
摘要翻译： 一种通过氮等离子体处理调节小宽度装置的鸟嘴形成引起的应力的方法。 氮等离子体工艺形成围绕沟槽壁的氮化物衬垫，其用于在随后的氧化步骤期间防止在隔离区中形成鸟嘴。 在一个实施例中，等离子体氮化处理发生在沟槽蚀刻之后，但在沟槽填充之前。 在另一个实施例中，等离子体氮化处理发生在沟槽填充之后。 在另一个实施例中，在等离子体氮化处理之前，在蚀刻的衬底的预定有效区域上形成块掩模。 该实施例用于保护PFET器件区域免受等离子体氮化处理，从而提供形成PFET器件区域的装置，其中由鸟嘴形成引起的应力增加了PFET的器件性能。
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