公开(公告)号：US20090200642A1

公开(公告)日：2009-08-13

申请号：US12028145

申请日：2008-02-08

申请人： Randy W. Mann ,  Jae-Eun Park ,  Richard Andre Wachnik

发明人： Randy W. Mann ,  Jae-Eun Park ,  Richard Andre Wachnik

IPC分类号： H01L29/93

CPC分类号： H01L29/93

摘要： An array of deep trenches is formed in a doped portion of the semiconductor substrate, which forms a lower electrode. A dielectric layer is formed on the sidewalls of the array of deep trenches. The array of deep trenches is filled with a doped semiconductor material to form an upper electrode comprising a top plate portion and a plurality of extension portions into the array of trenches. In a depletion mode, the bias condition across the dielectric layer depletes majority carriers within the top electrode, thus providing a low capacitance. In an accumulation mode, the bias condition attracts majority carriers toward the dielectric layer, providing a high capacitance. Thus, the trench metal-oxide-semiconductor (MOS) varactor provides a variable capacitance depending on the polarity of the bias.

摘要翻译： 在半导体衬底的掺杂部分中形成深沟槽阵列，形成下电极。 在深沟槽阵列的侧壁上形成介电层。 深沟槽阵列用掺杂半导体材料填充以形成上电极，其包括顶板部分和多个延伸部分到沟槽阵列中。 在耗尽模式中，跨越电介质层的偏置条件消耗顶部电极内的多数载流子，从而提供低电容。 在累积模式中，偏置条件吸引多数载流子朝向电介质层，提供高电容。 因此，沟槽金属氧化物半导体（MOS）变容二极管根据偏压的极性提供可变电容。

公开(公告)号：US07989922B2

公开(公告)日：2011-08-02

申请号：US12028145

申请日：2008-02-08

申请人： Randy W. Mann ,  Jae-Eun Park ,  Richard A. Wachnik

发明人： Randy W. Mann ,  Jae-Eun Park ,  Richard A. Wachnik

IPC分类号： H01L29/93

CPC分类号： H01L29/93

摘要： An array of deep trenches is formed in a doped portion of the semiconductor substrate, which forms a lower electrode. A dielectric layer is formed on the sidewalls of the array of deep trenches. The array of deep trenches is filled with a doped semiconductor material to form an upper electrode comprising a top plate portion and a plurality of extension portions into the array of trenches. In a depletion mode, the bias condition across the dielectric layer depletes majority carriers within the top electrode, thus providing a low capacitance. In an accumulation mode, the bias condition attracts majority carriers toward the dielectric layer, providing a high capacitance. Thus, the trench metal-oxide-semiconductor (MOS) varactor provides a variable capacitance depending on the polarity of the bias.

摘要翻译： 在半导体衬底的掺杂部分中形成深沟槽阵列，形成下电极。 在深沟槽阵列的侧壁上形成介电层。 深沟槽阵列用掺杂半导体材料填充以形成上电极，其包括顶板部分和多个延伸部分到沟槽阵列中。 在耗尽模式中，跨越电介质层的偏置条件消耗顶部电极内的多数载流子，从而提供低电容。 在累积模式中，偏置条件吸引多数载流子朝向电介质层，提供高电容。 因此，沟槽金属氧化物半导体（MOS）变容二极管根据偏压的极性提供可变电容。

公开(公告)号：US08626480B2

公开(公告)日：2014-01-07

申请号：US12574440

申请日：2009-10-06

申请人： Paul Chang ,  Jie Deng ,  Terrence B. Hook ,  Sim Y. Loo ,  Anda C. Mocuta ,  Jae-Eun Park ,  Kern Rim ,  Xiaojun Yu

发明人： Paul Chang ,  Jie Deng ,  Terrence B. Hook ,  Sim Y. Loo ,  Anda C. Mocuta ,  Jae-Eun Park ,  Kern Rim ,  Xiaojun Yu

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G01R31/2848 ,  G01R31/3008 ,  G06F17/5009 ,  G06F17/5022 ,  G06F17/5036

摘要： A system, method and computer program product for implementing a quiescent current leakage specific model into semiconductor device design and circuit design flows. The leakage model covers all device geometries with wide temperature and voltage ranges and, without the need for stacking factor calculations nor spread sheet based IDDQ calculations. The leakage model for IDDQ calculation incorporates further parasitic and proximity effects. The leakage model implements leakage calculations at different levels of testing, e.g., from a single device to a full chip design, and are integrated within one single model. The leakage model implements leakage calculations at different levels of testing with the leverage of a single switch setting. The implementation is via a hardware definition language code or object oriented code that can be compiled and operated using a netlist of interest, e.g., for conducting a performance analysis.

摘要翻译： 一种用于将静态电流泄漏特定模型实现为半导体器件设计和电路设计流程的系统，方法和计算机程序产品。 泄漏模型涵盖宽温度和电压范围的所有器件几何，并且不需要堆叠因子计算，也不需要基于平板的IDDQ计算。 IDDQ计算的泄漏模型包含进一步的寄生和邻近效应。 泄漏模型在不同的测试水平下实施泄漏计算，例如从单个设备到全芯片设计，并且集成在一个单一的模型中。 泄漏模型通过单个开关设置的杠杆来实现不同测试级别的泄漏计算。 该实现是通过硬件定义语言代码或面向对象的代码，其可以使用感兴趣的网表来编译和操作，例如用于进行性能分析。

公开(公告)号：US08237197B2

公开(公告)日：2012-08-07

申请号：US12831310

申请日：2010-07-07

申请人： Xiangdong Chen ,  Jie Deng ,  Weipeng Li ,  Deleep R. Nair ,  Jae-Eun Park ,  Daniel Tekleab ,  Xiaobin Yuan ,  Nam Sung Kim

发明人： Xiangdong Chen ,  Jie Deng ,  Weipeng Li ,  Deleep R. Nair ,  Jae-Eun Park ,  Daniel Tekleab ,  Xiaobin Yuan ,  Nam Sung Kim

IPC分类号： H01L29/66

CPC分类号： H01L21/823412 ,  H01L21/28202 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7835

摘要： A field effect transistor includes a partial SiGe channel, i.e., a channel including a SiGe channel portion, located underneath a gate electrode and a Si channel portion located underneath an edge of the gate electrode near the drain region. The SiGe channel portion can be located directly underneath a gate dielectric, or can be located underneath a Si channel layer located directly underneath a gate dielectric. The Si channel portion is located at the same depth as the SiGe channel portion, and contacts the drain region of the transistor. By providing a Si channel portion near the drain region, the GIDL current of the transistor is maintained at a level on par with the GIDL current of a transistor having a silicon channel only during an off state.

摘要翻译： 场效应晶体管包括部分SiGe沟道，即包括位于栅极下方的SiGe沟道部分的沟道部分，以及位于漏极区域附近的位于栅电极的边缘下方的Si沟道部分。 SiGe沟道部分可以位于栅极电介质的正下方，或者可以位于位于栅极电介质正下方的Si沟道层下方。 Si沟道部分位于与SiGe沟道部分相同的深度处，并与晶体管的漏极区域接触。 通过在漏极区附近提供Si沟道部分，晶体管的GIDL电流仅在断开状态下保持在与具有硅沟道的晶体管的GIDL电流相同的水平上。

公开(公告)号：US20110227136A1

公开(公告)日：2011-09-22

申请号：US12728488

申请日：2010-03-22

申请人： Jae-Eun Park ,  Weipeng Li ,  Deleep R. Nair ,  M. Dean Sciacca ,  Voon-Yew Thean ,  Ava Wan ,  Dong-Hun Lee ,  Yong-Meng Lee

发明人： Jae-Eun Park ,  Weipeng Li ,  Deleep R. Nair ,  M. Dean Sciacca ,  Voon-Yew Thean ,  Ava Wan ,  Dong-Hun Lee ,  Yong-Meng Lee

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7833 ,  H01L21/28518 ,  H01L21/76895 ,  H01L29/665 ,  H01L29/6659

摘要： The present disclosure provides a method of forming an electrical device. The method may begin with forming a gate structure on a substrate, in which a spacer is present in direct contact with a sidewall of the gate structure. A source region and a drain region is formed in the substrate. A metal semiconductor alloy is formed on the gate structure, an outer sidewall of the spacer and one of the source region and the drain region. An interlevel dielectric layer is formed over the metal semiconductor alloy. A via is formed through the interlevel dielectric stopping on the metal semiconductor alloy. An interconnect is formed to the metal semiconductor alloy in the via. The present disclosure also includes the structure produced by the method described above.

摘要翻译： 本公开提供了形成电气装置的方法。 该方法可以从衬底上形成栅极结构开始，其中间隔物直接与栅极结构的侧壁接触。 源极区和漏极区形成在衬底中。 在栅极结构上形成金属半导体合金，间隔物的外侧壁和源极区域和漏极区域中的一个。 在金属半导体合金上形成层间电介质层。 通过金属半导体合金上的层间电介质停止形成通孔。 在通孔中的金属半导体合金形成互连。 本公开还包括通过上述方法制造的结构。

公开(公告)号：US08563394B2

公开(公告)日：2013-10-22

申请号：US13083631

申请日：2011-04-11

申请人： Weipeng Li ,  Deleep R. Nair ,  Jae-Eun Park ,  Voon-Yew Thean ,  Young Way Teh

发明人： Weipeng Li ,  Deleep R. Nair ,  Jae-Eun Park ,  Voon-Yew Thean ,  Young Way Teh

IPC分类号： H01L21/76

CPC分类号： H01L21/823878 ,  H01L21/76232 ,  H01L21/823807

摘要： Solutions for forming an integrated circuit structure having a substantially planar N-P step height are disclosed. In one embodiment, a method includes: providing a structure having an n-type field effect transistor (NFET) region and a p-type field effect transistor (PFET) region; forming a mask over the PFET region to leave the NFET region exposed; performing dilute hydrogen-flouride (DHF) cleaning on the exposed NFET region to substantially lower an STI profile of the NFET region; and forming a silicon germanium (SiGE) channel in the PFET region after the performing of the DHF.

摘要翻译： 公开了用于形成具有基本平坦的N-P台阶高度的集成电路结构的解决方案。 在一个实施例中，一种方法包括：提供具有n型场效应晶体管（NFET）区域和p型场效应晶体管（PFET）区域的结构; 在PFET区域上形成掩模以使NFET区域露出; 在暴露的NFET区域上进行稀释的氟化氢（DHF）清洁以显着降低NFET区域的STI分布; 以及在执行DHF之后在PFET区域中形成硅锗（SiGE）通道。

公开(公告)号：US20050233598A1

公开(公告)日：2005-10-20

申请号：US11107559

申请日：2005-04-15

申请人： Hyung-Suk Jung ,  Jong-Ho Lee ,  Ha-Jin Lim ,  Jae-Eun Park ,  Yun-Seok Kim ,  Jong-Ho Yang

发明人： Hyung-Suk Jung ,  Jong-Ho Lee ,  Ha-Jin Lim ,  Jae-Eun Park ,  Yun-Seok Kim ,  Jong-Ho Yang

IPC分类号： H01L21/31 ,  C23C16/40 ,  H01L21/28 ,  H01L21/314 ,  H01L21/336 ,  H01L21/469 ,  H01L29/51

CPC分类号： H01L21/022 ,  C23C16/402 ,  C23C16/45525 ,  C23C16/45527 ,  C23C16/45529 ,  H01L21/0228 ,  H01L21/02318 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/3142 ,  H01L21/3143 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： Methods of fabricating high-k dielectric layers having reduced impurities for use in semiconductor applications are disclosed. The methods include the steps of: forming a stacked dielectric layer having a first dielectric layer and a second dielectric layer formed on a semiconductor substrate using an ALD method, in combination with a post-treatment step performed to the stacked dielectric layer. The steps of forming the stacked dielectric layer and performing the post-treatment are repeated at least once, thereby fabricating the high-k dielectric layer.

摘要翻译： 公开了制造用于半导体应用的具有减少的杂质的高k电介质层的方法。 该方法包括以下步骤：结合对叠层电介质层执行的后处理步骤，使用ALD法形成具有形成在半导体衬底上的第一电介质层和第二电介质层的叠层电介质层。 形成堆叠的电介质层并进行后处理的步骤至少重复一次，从而制造高k电介质层。

公开(公告)号：US08120058B2

公开(公告)日：2012-02-21

申请号：US12607116

申请日：2009-10-28

申请人： Jae-Eun Park ,  Xinlin Wang ,  Xiangdong Chen

发明人： Jae-Eun Park ,  Xinlin Wang ,  Xiangdong Chen

IPC分类号： H01L29/739

CPC分类号： H01L29/7394 ,  H01L29/66325

摘要： A method of forming a semiconductor device having an asymmetrical source and drain. In one embodiment, the method includes forming a gate structure on a first portion of the substrate having a well of a first conductivity. A source region of a second conductivity and drain region of the second conductivity is formed within the well of the first conductivity in a portion of the substrate that is adjacent to the first portion of the substrate on which the gate structure is present. A doped region of a second conductivity is formed within the drain region to provide an integrated bipolar transistor on a drain side of the semiconductor device, in which a collector is provided by the well of the first conductivity, the base is provided by the drain region of the second conductivity and the emitter is provided by the doped region of the second conductivity that is present in the drain region. A semiconductor device formed by the above-described method is also provided.

摘要翻译： 一种形成具有不对称源极和漏极的半导体器件的方法。 在一个实施例中，该方法包括在具有第一导电性阱的衬底的第一部分上形成栅极结构。 第二导电性的第二导电性和漏极区的源极区域形成在第一导电性的阱内，在与存在栅极结构的基板的第一部分相邻的基板的一部分中。 在漏极区域内形成第二导电性的掺杂区域，以在半导体器件的漏极侧提供集成的双极晶体管，其中集电极由第一导电性的阱提供，基极由漏极区域 的第二导电性和发射极由存在于漏极区域中的第二导电性的掺杂区域提供。 还提供了通过上述方法形成的半导体器件。

公开(公告)号：US07939894B2

公开(公告)日：2011-05-10

申请号：US12185368

申请日：2008-08-04

申请人： Terence B. Hook ,  Jenny Hu ,  Jae-Eun Park

发明人： Terence B. Hook ,  Jenny Hu ,  Jae-Eun Park

IPC分类号： H01L21/70

CPC分类号： H01L27/0738 ,  H01L29/78

摘要： The present invention provides a method of controlling bias in an electrical device including providing semiconductor devices on a bulk semiconductor substrate each including an active body region that is isolated from the active body region of adjacent devices, and providing a body resistor in electrical contact with the active body region of the bulk semiconductor substrate, wherein the body resistor provides for adjustability of the body potential of the semiconductor devices. In another aspect the present invention provides a semiconductor device including a bulk semiconductor substrate, at least one field effect transistor formed on the bulk semiconductor substrate including an isolated active body region, and a resistor in electrical communication with the isolated active body region.

摘要翻译： 本发明提供了一种控制电气装置中的偏置的方法，包括提供在体半导体衬底上的半导体器件，每个半导体器件包括与相邻器件的有源体区隔离的有源体区域，以及提供与电极接触的体电阻器 活体体区域，其中体电阻器提供半导体器件的体电位的可调节性。 在另一方面，本发明提供了一种半导体器件，其包括体半导体衬底，形成在包括隔离的有源体区域的体半导体衬底上的至少一个场效应晶体管和与隔离的有源体区域电连通的电阻器。

公开(公告)号：US20110095333A1

公开(公告)日：2011-04-28

申请号：US12607116

申请日：2009-10-28

申请人： Jae-Eun Park ,  Xinlin Wang ,  Xiangdong Chen

发明人： Jae-Eun Park ,  Xinlin Wang ,  Xiangdong Chen

IPC分类号： H01L29/739 ,  H01L21/331

CPC分类号： H01L29/7394 ,  H01L29/66325

摘要： A method of forming a semiconductor device having an asymmetrical source and drain. In one embodiment, the method includes forming a gate structure on a first portion of the substrate having a well of a first conductivity. A source region of a second conductivity and drain region of the second conductivity is formed within the well of the first conductivity in a portion of the substrate that is adjacent to the first portion of the substrate on which the gate structure is present. A doped region of a second conductivity is formed within the drain region to provide an integrated bipolar transistor on a drain side of the semiconductor device, in which a collector is provided by the well of the first conductivity, the base is provided by the drain region of the second conductivity and the emitter is provided by the doped region of the second conductivity that is present in the drain region. A semiconductor device formed by the above-described method is also provided.

摘要翻译： 一种形成具有不对称源极和漏极的半导体器件的方法。 在一个实施例中，该方法包括在具有第一导电性阱的衬底的第一部分上形成栅极结构。 第二导电性的第二导电性和漏极区的源极区域形成在第一导电性的阱内，在与存在栅极结构的基板的第一部分相邻的基板的一部分中。 在漏极区域内形成第二导电性的掺杂区域，以在半导体器件的漏极侧提供集成的双极晶体管，其中集电极由第一导电性的阱提供，基极由漏极区域 的第二导电性和发射极由存在于漏极区域中的第二导电性的掺杂区域提供。 还提供了通过上述方法形成的半导体器件。