公开(公告)号：US12072761B2

公开(公告)日：2024-08-27

申请号：US17831436

申请日：2022-06-02

Applicant: Micron Technology, Inc.

Inventor： Daniele Balluchi

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1004 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0688

Abstract: Systems, apparatuses, and methods related to addressing for data and additional data portions are described herein. In an example method, addressing for data and additional data portions can include accessing data written to a memory device in response to receipt of a first command configured according to a nondeterministic memory interface protocol. The first command can be a compute express link (CXL) protocol compliant command. The example method can further include converting an address associated with the first command to a second command configured according to a standardized deterministic memory interface protocol. The second command can be a DRAM accessible command. The example method can further include accessing a page of memory cells of the memory device in which the data is written, and in which additional data portions associated with the data are written using the converted address associated with the first command.

公开(公告)号：US12001706B2

公开(公告)日：2024-06-04

申请号：US17854639

申请日：2022-06-30

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Angelo Visconti ,  Giorgio Servalli ,  Daniele Balluchi ,  Paolo Amato

IPC: G06F3/06

CPC classification number: G06F3/0652 ,  G06F3/0616 ,  G06F3/0673

Abstract: Provided is a computing system including a memory system in communication with a host, to store data therein. The memory system includes a memory having a plurality of memory components coupled to the controller via a memory interface; and a memory controller configured to communicate with the memory to control data transmission and performing scrubbing operation of the memory components and detecting a region of the memory to be sanitized and performing a sanitization operation of the detected region to prevent the occurrence of failure.

公开(公告)号：US11994946B2

公开(公告)日：2024-05-28

申请号：US17752538

申请日：2022-05-24

Applicant: Micron Technology, Inc.

Inventor： Paolo Amato ,  Marco Sforzin ,  Daniele Balluchi

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/1068 ,  G06F11/076 ,  G06F11/0772 ,  G06F11/1004

Abstract: Systems, apparatuses, and methods related to memory bank protection are described. A quantity of errors within a single memory bank is determined and the determined quantity is used to further determine whether to access other memory banks to correct the determined quantity. The memory bank protection described herein avoids a single memory bank of a memory die being a single point of failure (SPOF).

公开(公告)号：US11804271B2

公开(公告)日：2023-10-31

申请号：US17726351

申请日：2022-04-21

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Umberto Di Vincenzo ,  Daniele Balluchi

IPC: G11C11/00 ,  G11C16/30 ,  G11C16/04

CPC classification number: G11C16/30 ,  G11C16/0483

Abstract: Methods, systems, and devices for operational modes for reduced power consumption in a memory system are described. A memory device may be coupled with a capacitor of a power management integrated circuit (PMIC). The memory device may operate in a first mode where a supply voltage is provided to the memory device from the PMIC. The memory device may operate in a second mode where it is isolated from the PMIC. When isolated, a node of the memory device (e.g., an internal node) may be discharged while the capacitor of the PMIC remains charged. When the memory device resumes operating in the first mode, a supply voltage may be provided to it based on the residual charge of the capacitor.

公开(公告)号：US20220382630A1

公开(公告)日：2022-12-01

申请号：US17752538

申请日：2022-05-24

Applicant: Micron Technology, Inc.

Inventor： Paolo Amato ,  Marco Sforzin ,  Daniele Balluchi

IPC: G06F11/10 ,  G06F11/07

Abstract: Systems, apparatuses, and methods related to memory bank protection are described. A quantity of errors within a single memory bank can be determined and the determined quantity can be used to further determine whether to access other memory banks to correct the determined quantity. The memory bank protection described herein can avoid a single memory bank of a memory die being a single point of failure (SPOF).

公开(公告)号：US20220357791A1

公开(公告)日：2022-11-10

申请号：US17870696

申请日：2022-07-21

Applicant: Micron Technology, Inc.

Inventor： Greg Blodgett ,  Daniele Balluchi ,  Danilo Caraccio ,  Graziano Mirichigni

IPC: G06F1/3234 ,  G06F13/16 ,  G11C5/14

Abstract: The present disclosure includes apparatuses and methods for providing energy information to memory. An embodiment includes determining, by a host, that a charge level of an energy source coupled to the host has reached or exceeded a threshold value, and transmitting, from the host to a memory device coupled to the host, signaling indicative of an energy mode for the memory device, wherein the signaling is transmitted based at least in part on determining that the charge level of the energy source has reached or exceeded the threshold.

公开(公告)号：US20220100244A1

公开(公告)日：2022-03-31

申请号：US17033583

申请日：2020-09-25

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Paolo Amato ,  Ferdinando Bedeschi ,  Daniele Balluchi

IPC: G06F1/26

Abstract: Methods, systems, and devices for a memory system with centralized power management are described. A memory system may include memory devices and a power management circuit. The memory devices may use one or more supply voltages during operation of the memory devices, which may include supply voltages received from an external device and high supply voltages generated within the memory system. The power management circuit may receive supply voltages from the external device and generate the supply voltages to the memory devices. The memory devices may exclude charge pump circuitry for generating supply voltages and may instead include pads for receiving the supply voltages from the power management circuit, in some examples. The memory system may include a controller that is configured to determine an amount of power to provide to the memory devices and transmit an indication of the amount of power to the power management circuit.

公开(公告)号：US11194708B2

公开(公告)日：2021-12-07

申请号：US16793185

申请日：2020-02-18

Applicant: Micron Technology, Inc.

Inventor： Paolo Amato ,  Daniele Balluchi

IPC: G06F12/02 ,  G06F1/3206 ,  G11C16/34 ,  G06F3/06

Abstract: The present disclosure includes apparatuses, methods, and systems for data relocation in memory having two portions of data. An embodiment includes a memory having a plurality of physical blocks of memory cells, and a first and second portion of data having a first and second, respectively, number of logical block addresses associated therewith. Two of the plurality of physical blocks of cells do not have data stored therein. Circuitry is configured to relocate the data of the first portion that is associated with one of the first number of logical block addresses to one of the two physical blocks of cells that don't have data stored therein, and relocate the data of the second portion that is associated with one of the second number of logical block addresses to the other one of the two physical blocks of cells that don't have data stored therein.

公开(公告)号：US20210349830A1

公开(公告)日：2021-11-11

申请号：US17385380

申请日：2021-07-26

Applicant: Micron Technology, Inc.

Inventor： Daniele Balluchi ,  Dionisio Minopoli

IPC: G06F12/1009

Abstract: Logical to physical tables each including logical to physical address translations for first logical addresses can be stored. Logical to physical table fragments each including logical to physical address translations for second logical address can be stored. A first level index can be stored. The first level index can include a physical table address of a respective one of the logical to physical tables for each of the first logical addresses and a respective pointer to a second level index for each of the second logical addresses. The second level index can be stored and can include a physical fragment address of a respective logical to physical table fragment for each of the second logical addresses.

公开(公告)号：US20210240395A1

公开(公告)日：2021-08-05

申请号：US17234103

申请日：2021-04-19

Applicant: Micron Technology, Inc.

Inventor： Daniele Balluchi ,  Paolo Amato

IPC: G06F3/06 ,  G06F11/07

Abstract: An apparatus can have an array of memory cells and a controller coupled to the array. The controller can be configured to read a group sentinel cells of the array and without reading a number of other groups of cells of the array to determine that data stored in the number of other groups of cells lacks integrity based on a determination that data stored in the group of sentinel cells lacks integrity.