公开(公告)号：US20160329090A1

公开(公告)日：2016-11-10

申请号：US14707878

申请日：2015-05-08

Applicant: Micron Technology, Inc.

Inventor： Dean Gans ,  Moo Sung Chae ,  Daniel Skinner

IPC: G11C11/4076 ,  G11C11/4096

CPC classification number: G11C11/4076 ,  G11C7/062 ,  G11C7/1006 ,  G11C7/14 ,  G11C7/222 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/2254

Abstract: A memory channel including an internal clock circuit is disclosed. The clock circuit may synthesize an internal clock signal for use by one or more components of the memory channel. The internal clock signal may have a different frequency than an external clock frequency. The memory channel may include multiple clock circuits that generate multiple internal clock signals. Each portion of the memory channel associated with a different clock circuit may be phase and/or frequency independent of the other portions of the memory channel. The clock circuit may synthesize an internal clock signal based on an external clock signal. The clock circuit may use encoded timing data from an encoded I/O scheme to align the phase of the internal clock signal to a data signal.

Abstract translation: 公开了一种包括内部时钟电路的存储通道。 时钟电路可以合成内部时钟信号以供存储器通道的一个或多个组件使用。 内部时钟信号可能具有与外部时钟频率不同的频率。 存储器通道可以包括产生多个内部时钟信号的多个时钟电路。 与不同时钟电路相关联的存储器通道的每个部分可以是与存储器通道的其它部分无关的相位和/或频率。 时钟电路可以基于外部时钟信号合成内部时钟信号。 时钟电路可以使用来自编码I / O方案的编码定时数据将内部时钟信号的相位对准数据信号。

公开(公告)号：US12019570B2

公开(公告)日：2024-06-25

申请号：US18149817

申请日：2023-01-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kang-Yong Kim ,  Dean Gans

IPC: G06F13/16 ,  G06F9/30 ,  G06F12/02 ,  G11C7/22 ,  G11C16/08 ,  G11C16/32 ,  G11C29/02

CPC classification number: G06F13/1689 ,  G06F9/30145 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028

Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. A controller provides a memory system with memory commands to access memory. The commands are decoded to provide internal signals and commands for performing operations, such as operations to access the memory array. The memory commands provided for accessing memory may include timing command and access commands. Examples of access commands include a read command and a write command. Timing commands may be used to control the timing of various operations, for example, for a corresponding access command. The timing commands may include opcodes that set various modes of operation during an associated access operation for an access command.

公开(公告)号：US11728812B2

公开(公告)日：2023-08-15

申请号：US17444771

申请日：2021-08-10

Applicant: Micron Technology, Inc.

Inventor： Dean Gans

IPC: H03K19/0185 ,  G11C29/02 ,  G11C29/50 ,  G11C7/02 ,  G06F13/40 ,  H03K19/00 ,  G11C7/04 ,  G11C29/44

CPC classification number: H03K19/018585 ,  G06F13/4086 ,  G11C7/02 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50008 ,  H03K19/0005 ,  G11C7/04 ,  G11C2029/4402 ,  G11C2207/2254

Abstract: Apparatuses and methods for identifying memory devices of a semiconductor device sharing an external resistance are disclosed. A memory device of a semiconductor device may be set in an identification mode and provide an identification request to other memory devices that are coupled to a common communication channel. The memory devices that are coupled to the common communication channel may share an external resistance, for example, for calibration of respective programmable termination components of the memory devices. The memory devices that receive the identification request set a respective identification flag which can be read to determine which memory devices share an external resistance with the memory device having the set identification mode.

公开(公告)号：US20230137651A1

公开(公告)日：2023-05-04

申请号：US18047373

申请日：2022-10-18

Applicant: Micron Technology, Inc.

Inventor： Dean Gans

IPC: H03H11/28 ,  G11C7/10 ,  H03K19/00 ,  G11C29/02

Abstract: Apparatuses and methods for calibrating adjustable impedances of a semiconductor device are disclosed in the present application. An example apparatus includes a register configured to store impedance calibration information and further includes programmable termination resistances having a programmable impedance. The example apparatus further includes an impedance calibration circuit configured to perform a calibration operation to determine calibration parameters for setting the programmable impedance of the programmable termination resistances. The impedance calibration circuit is further configured to program the impedance calibration information in the register related to the calibration operation.

公开(公告)号：US20220035539A1

公开(公告)日：2022-02-03

申请号：US17444771

申请日：2021-08-10

Applicant: Micron Technology, Inc.

Inventor： Dean Gans

IPC: G06F3/06

Abstract: Apparatuses and methods for identifying memory devices of a semiconductor device sharing an external resistance are disclosed. A memory device of a semiconductor device may be set in an identification mode and provide an identification request to other memory devices that are coupled to a common communication channel. The memory devices that are coupled to the common communication channel may share an external resistance, for example, for calibration of respective programmable termination components of the memory devices. The memory devices that receive the identification request set a respective identification flag which can be read to determine which memory devices share an external resistance with the memory device having the set identification mode.

公开(公告)号：US10915474B2

公开(公告)日：2021-02-09

申请号：US16035414

申请日：2018-07-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kang-Yong Kim ,  Dean Gans

IPC: G06F13/16 ,  G11C29/02 ,  G11C7/22 ,  G06F9/30 ,  G11C16/32 ,  G11C16/08 ,  G06F12/02

Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. A controller provides a memory system with memory commands to access memory. The commands are decoded to provide internal signals and commands for performing operations, such as operations to access the memory array. The memory commands provided for accessing memory may include timing command and access commands. Examples of access commands include a read command and a write command. Timing commands may be used to control the timing of various operations, for example, for a corresponding access command. The timing commands may include opcodes that set various modes of operation during an associated access operation for an access command.

公开(公告)号：US10789186B2

公开(公告)日：2020-09-29

申请号：US16657474

申请日：2019-10-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kang-Yong Kim ,  Dean Gans

IPC: G06F13/16 ,  G06F9/30 ,  G11C7/22 ,  G11C29/02

Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. A controller provides a memory system with memory commands to access memory. The commands are decoded to provide internal signals and commands for performing operations, such as operations to access the memory array. The memory commands provided for accessing memory may include timing command and access commands. Examples of access commands include a read command and a write command. Timing commands may be used to control the timing of various operations, for example, for a corresponding access command. The timing commands may include opcodes that set various modes of operation during an associated access operation for an access command.

公开(公告)号：US20200287778A1

公开(公告)日：2020-09-10

申请号：US16881337

申请日：2020-05-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Timothy M. Hollis ,  Dean Gans ,  Randon Richards ,  Bruce W. Schober

IPC: H04L12/24 ,  H04L12/863 ,  G06F13/00 ,  G11C7/10 ,  H04L25/03

Abstract: According to one embodiment, a data buffer is described. The data buffer comprises a first input/output circuit configured to receive and provide a first signal encoded according to a first communications protocol, a second input/output circuit configured to receive and provide a second signal encoded according to a second communications protocol, and a conversion circuit coupled to the first and second input/output circuits and configured to convert the first signal to the second signal and to convert the second signal to the first signal.

公开(公告)号：US20200050564A1

公开(公告)日：2020-02-13

申请号：US16657474

申请日：2019-10-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kang-Yong Kim ,  Dean Gans

IPC: G06F13/16 ,  G11C7/22 ,  G06F9/30

Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. A controller provides a memory system with memory commands to access memory. The commands are decoded to provide internal signals and commands for performing operations, such as operations to access the memory array. The memory commands provided for accessing memory may include timing command and access commands. Examples of access commands include a read command and a write command. Timing commands may be used to control the timing of various operations, for example, for a corresponding access command. The timing commands may include opcodes that set various modes of operation during an associated access operation for an access command.

公开(公告)号：US10387341B2

公开(公告)日：2019-08-20

申请号：US16193286

申请日：2018-11-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dean Gans ,  Bruce Schober ,  Moo Sung Chae

IPC: G06F13/16 ,  G06F13/40

Abstract: Apparatuses and methods for asymmetric input output interfaces for memory are disclosed. An example apparatus may include a receiver and a transmitter. The receiver may be configured to receive first data signals having a first voltage swing and having a first slew rate. The transmitter may be configured to provide second data signals having a second voltage swing and having a second slew rate, wherein the first and second voltage swings are different, and wherein the first and second slew rates are different.