公开(公告)号：US20240243072A1

公开(公告)日：2024-07-18

申请号：US18408194

申请日：2024-01-09

Applicant: Micron Technology, Inc.

Inventor： Kar Wui Thong ,  Harsh Narendrakumar Jain ,  Richard T. Housley ,  Manampurathu Sivaramapanicker Suresh Kumar

IPC: H01L23/544

CPC classification number: H01L23/544 ,  H01L2223/54426 ,  H01L2223/5446 ,  H10B43/27

Abstract: A method used in forming integrated circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The first tiers comprise sacrificial material and the second tiers comprise non-sacrificial material that is of different composition from that of the sacrificial material. The stack extends from individual die areas to and across scribe-line area that is between immediately-adjacent of the individual die areas. The scribe-line area comprises a horizontal area in which a registration mark or an alignment mark is being fabricated. Horizontally-spaced features of the registration mark or of the alignment mark are simultaneously formed in the first tiers and the second tiers in the horizontal area and in the individual die areas. The horizontally-spaced features in the horizontal area are grouped in sections that are horizontally-separated by gaps in at least one vertical cross-section where there are less, if any, such horizontally-spaced features than are in the sections. Horizontally-spaced vertical slots are formed through uppermost of the first and second tiers of the stack in the horizontal area of the registration mark or of the alignment mark. Through the horizontally-spaced vertical slots, the sacrificial material is replaced with metal material. After the replacing, the first and second tiers in the scribe-line areas are cut through to form individual die that individually comprise one of the individual die areas. Other embodiments, including structure, are disclosed.

公开(公告)号：US20240071930A1

公开(公告)日：2024-02-29

申请号：US18504901

申请日：2023-11-08

Applicant: Micron Technology, Inc.

Inventor： Harsh Narendrakumar Jain

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L23/53295 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: A microelectronic device comprises a first deck structure comprising alternating conductive structures and insulating structures arranged in tiers, each of the tiers individually comprising one of the conductive structures and one of the insulating structures, a second deck structure vertically overlying the first deck structure and comprising additional tiers of the conductive structures and insulative structures, a staircase structure within the first deck structure and having steps comprising edges of the tiers, a dielectric material covering the steps of the staircase structure and extending through the first deck structure, and a liner material interposed between the steps of the staircase structure and terminating at an interdeck region between the first deck structure and the second deck structure. Related microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：US20230317604A1

公开(公告)日：2023-10-05

申请号：US17657264

申请日：2022-03-30

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Harsh Narendrakumar Jain ,  Indra V. Chary ,  Umberto Maria Meotto ,  Paolo Tessariol

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L21/76816 ,  H01L21/76877

Abstract: Microelectronic devices include a stack structure having a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A series of stadiums, within the stack structure, includes stadiums of differing numbers of staircase sets, such as a stadium having multiple parallel sets of staircases and an additional stadium having a single set of staircases. Each of the staircases comprises steps, at ends of the conductive structures, with a same multi-tier riser height. In methods of fabrication, a same initial stadium opening may be concurrently formed for each of the stadiums—regardless of whether the stadium is to include the single set or the multiple parallel sets of staircases—with the steps of the same multi-tier riser height. Electronic systems are also disclosed.

公开(公告)号：US11682581B2

公开(公告)日：2023-06-20

申请号：US17127823

申请日：2020-12-18

Applicant: Micron Technology, Inc.

Inventor： Kar Wui Thong ,  Harsh Narendrakumar Jain ,  John Hopkins

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H10B43/27 ,  H10B41/27 ,  H01L27/11582 ,  H01L27/11556

CPC classification number: H01L21/76897 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11582

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes levels of conductive materials interleaved with levels of dielectric materials; memory cell strings including respective pillars extending through the levels of conductive materials and the levels of dielectric materials; a dielectric structure formed in a slit, the slit extending through the levels of conductive materials and the levels of dielectric materials, the dielectric structure separating the levels of conductive materials and the levels of dielectric materials into a first portion and a second portion; first conductive structures located over and coupled to respective pillars of the first memory cell strings; second conductive structures located over and coupled to respective pillars of the second memory cell strings; and a conductive line contacting the dielectric structure, a conductive structure of the first conductive structures, and a conductive structure of the second conductive structures.

公开(公告)号：US11641741B2

公开(公告)日：2023-05-02

申请号：US17016039

申请日：2020-09-09

Applicant: Micron Technology, Inc.

Inventor： Kaiming Luo ,  Sarfraz Qureshi ,  Md Zakir Ullah ,  Jessica Jing Wen Low ,  Harsh Narendrakumar Jain ,  Kok Siak Tang ,  Indra V. Chary ,  Matthew J. King

IPC: H01L27/11521 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11568

Abstract: Microelectronic devices include a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A series of slit structures extends through the stack structure and divides the stack structure into a series of blocks. In a progressed portion of the series of blocks, each block comprises an array of pillars extending through the stack structure of the block. Also, each block—in the progressed portion—has a different block width than a block width of a neighboring block of the progressed portion of the series of blocks. At least one pillar, of the pillars of the array of pillars in the progressed portion, exhibits bending. Related methods and electronic systems are also disclosed.

公开(公告)号：US20220302148A1

公开(公告)日：2022-09-22

申请号：US17205954

申请日：2021-03-18

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Sidhartha Gupta ,  Kar Wui Thong ,  Harsh Narendrakumar Jain

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/06 ,  H01L29/66 ,  H01L29/78

Abstract: A method of forming a microelectronic device including a first stack structure comprising alternating levels of insulative structures and other insulative structures, forming strings of memory cells through the first stack structure, forming a second stack structure over the first stack structure, based at least partially on observed amount of pillar bending within the first stack structure, forming a first tailored reticle specific to the observed amount of pillar bending, utilizing the first tailored reticle to form openings extending through the second stack structure and over some of the strings of memory cells, wherein centers of the openings over the strings of memory cells are at least substantially aligned with the centers of uppermost surfaces of the strings of memory cells in a direction of the observed pillar bending, and forming upper pillars extending through the second stack structure and over some of the strings of memory cells.

公开(公告)号：US20220231031A1

公开(公告)日：2022-07-21

申请号：US17153740

申请日：2021-01-20

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Shuangqiang Luo ,  Harsh Narendrakumar Jain ,  Nancy M. Lomeli ,  Christopher J. Larsen

IPC: H01L27/1157 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573 ,  H01L23/00 ,  H01L23/528 ,  H01L23/522

Abstract: A method of forming a microelectronic device includes forming a microelectronic device structure. The microelectronic device structure includes a stack structure having an alternating sequence of conductive structures and insulative structures, an upper stadium structure, a lower stadium structure, and a crest region defined between a first stair step structure of the upper stadium structure and a second stair step structure of the lower stadium structure. The stack structure further includes pillar structures extending through the stack structure and dielectric structures interposed between neighboring pillar structures within the upper stadium structure. The method further includes forming a trench in the crest region of the stack structure between two dielectric structures of the dielectric structures on opposing sides of another dielectric structure and filling the trench with a dielectric material. The trench partially overlaps with the dielectric structures.

公开(公告)号：US20220199467A1

公开(公告)日：2022-06-23

申请号：US17127823

申请日：2020-12-18

Applicant: Micron Technology, Inc.

Inventor： Kar Wui Thong ,  Harsh Narendrakumar Jain ,  John Hopkins

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11582

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes levels of conductive materials interleaved with levels of dielectric materials; memory cell strings including respective pillars extending through the levels of conductive materials and the levels of dielectric materials; a dielectric structure formed in a slit, the slit extending through the levels of conductive materials and the levels of dielectric materials, the dielectric structure separating the levels of conductive materials and the levels of dielectric materials into a first portion and a second portion; first conductive structures located over and coupled to respective pillars of the first memory cell strings; second conductive structures located over and coupled to respective pillars of the second memory cell strings; and a conductive line contacting the dielectric structure, a conductive structure of the first conductive structures, and a conductive structure of the second conductive structures.

公开(公告)号：US20220130954A1

公开(公告)日：2022-04-28

申请号：US17078755

申请日：2020-10-23

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Indra V. Chary ,  Harsh Narendrakumar Jain

IPC: H01L29/06 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/522

Abstract: A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, a staircase structure within the stack structure having steps comprising horizontal edges of the tiers, a first insulative material vertically overlying the staircase structure, conductive contact structures comprising a conductive material extending through the first insulative material and in contact with the steps of the staircase structure, and a second insulative material extending in a first horizontal direction between horizontally neighboring conductive contact structures and exhibiting one or more different properties than the first insulative material. Related microelectronic devices, electronic systems, and methods are also described.