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    Apparatuses and methods for scatter and gather
    41.
    发明授权
    Apparatuses and methods for scatter and gather 有权

    公开(公告)号：US10964358B2

    公开(公告)日：2021-03-30

    申请号：US16536941

    申请日：2019-08-09

    Applicant: Micron Technology, Inc.

    Inventor： Jason T. Zawodny ,  Kelley D. Dobelstein ,  Timothy P. Finkbeiner ,  Richard C. Murphy

    IPC: G11C11/4096 ,  G11C11/4091 ,  G06F3/06 ,  G11C7/10 ,  G11C8/12 ,  G11C7/06 ,  G11C11/408

    Abstract: The present disclosure includes apparatuses and methods related to scatter/gather in a memory device. An example apparatus comprises a memory device that includes an array of memory cells, sensing circuitry, and a memory controller coupled to one another. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A channel controller is configured to receive a block of instructions, the block of instructions including individual instructions for at least one of a gather operation and a scatter operation. The channel controller is configured to send individual instructions to the memory device and to control the memory controller such that the at least one of the gather operation and the scatter operation is executed on the memory device based on a corresponding one of the individual instructions.

    Apparatuses and methods for compute components formed over an array of memory cells
    42.
    发明授权
    Apparatuses and methods for compute components formed over an array of memory cells 有权

    公开(公告)号：US10854269B2

    公开(公告)日：2020-12-01

    申请号：US16526198

    申请日：2019-07-30

    Applicant: Micron Technology, Inc.

    Inventor： Jason T. Zawodny

    IPC: G11C11/402 ,  G11C11/406 ,  G11C11/403 ,  G11C5/02 ,  G11C7/10 ,  G11C11/407

    Abstract: The present disclosure includes apparatuses and methods related to compute components formed over an array of storage elements. An example apparatus comprises a base substrate material and an array of memory cells formed over the base substrate material. The array can include a plurality of access transistors comprising a first semiconductor material. A compute component can be formed over and coupled to the array. The compute component can include a plurality of compute transistors comprising a second semiconductor material. The second semiconductor material can have a higher concentration of doping ions than the first semiconductor material.

    Apparatuses and methods for performing corner turn operations using sensing circuitry
    43.
    发明授权
    Apparatuses and methods for performing corner turn operations using sensing circuitry 有权

    公开(公告)号：US10699756B2

    公开(公告)日：2020-06-30

    申请号：US16215122

    申请日：2018-12-10

    Applicant: Micron Technology, Inc.

    Inventor： Jason T. Zawodny ,  Sanjay Tiwari

    IPC: G11C7/10 ,  G11C7/06 ,  G11C8/16 ,  G11C8/10 ,  G11C15/04

    Abstract: The present disclosure includes apparatuses and methods related to performing corner turn operations using sensing circuitry. An example apparatus comprises a first group of memory cells coupled to an access line and a plurality of sense lines and a second group of memory cells coupled to a plurality of access lines and one of the plurality of sense lines. The access line can be a same access line as one of the plurality of access lines. The example apparatus comprises a controller configured to cause a corner turn operation on an element stored in the first group of memory cells resulting in the element being stored in the second group of memory cells to be performed using sensing circuitry.

    DATA TRANSFER BETWEEN SUBARRAYS IN MEMORY
    46.
    发明申请
    DATA TRANSFER BETWEEN SUBARRAYS IN MEMORY 审中-公开

    公开(公告)号：US20190034116A1

    公开(公告)日：2019-01-31

    申请号：US16138287

    申请日：2018-09-21

    Applicant: Micron Technology, Inc.

    Inventor： Jason T. Zawodny ,  Glen E. Hush ,  Richard C. Murphy

    IPC: G06F3/06 ,  G11C11/4091

    CPC classification number: G11C7/06 ,  G06F3/0647 ,  G11C5/025 ,  G11C7/1006 ,  G11C11/4091

    Abstract: The present disclosure includes apparatuses and methods for data transfer between subarrays in memory. An example may include a first subarray of memory cells and a second subarray of memory cells, wherein a first portion of memory cells of the first subarray and a first portion of memory cells of the second subarray are coupled to a first sensing circuitry stripe. A third subarray of memory cells can include a first portion of memory cells coupled to a second sensing circuitry stripe. A second portion of memory cells of the second subarray and a second portion of memory cells of the third subarray can be coupled to a third sensing circuitry stripe. A particular row of the second array can include memory cells from the first portion of memory cells in the second array coupled to memory cells from the second portion of memory cells in the second array.

    APPARATUSES AND METHODS FOR SCATTER AND GATHER
    47.
    发明申请
    APPARATUSES AND METHODS FOR SCATTER AND GATHER 审中-公开

    公开(公告)号：US20170337953A1

    公开(公告)日：2017-11-23

    申请号：US15669300

    申请日：2017-08-04

    Applicant: Micron Technology, Inc.

    Inventor： Jason T. Zawodny ,  Kelley D. Dobelstein ,  Timothy P. Finkbeiner ,  Richard C. Murphy

    IPC: G11C7/10 ,  G11C8/12 ,  G06F3/06 ,  G11C11/4096

    Abstract: The present disclosure includes apparatuses and methods related to scatter/gather in a memory device. An example apparatus comprises a memory device that includes an array of memory cells, sensing circuitry, and a memory controller coupled to one another. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A channel controller is configured to receive a block of instructions, the block of instructions including individual instructions for at least one of a gather operation and a scatter operation. The channel controller is configured to send individual instructions to the memory device and to control the memory controller such that the at least one of the gather operation and the scatter operation is executed on the memory device based on a corresponding one of the individual instructions.

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