公开(公告)号：US20210011796A1

公开(公告)日：2021-01-14

申请号：US17036973

申请日：2020-09-29

Applicant: Micron Technology, Inc.

Inventor： Jonathan Scott Parry ,  Nadav Grosz

IPC: G06F11/07 ,  G06F9/445 ,  G06F1/3287 ,  G06F1/3225 ,  G06F1/3228 ,  G06F1/3237

Abstract: Apparatus and methods are disclosed, including determining whether firmware has been successfully loaded and whether the firmware version is valid and operable, and if the firmware has not been successfully loaded or the firmware is not valid and operable, tracking a number of unsuccessful attempts to load the firmware or an elapsed time for unsuccessful attempts to load the firmware, and entering a memory device into a reduced-power state if either the number of unsuccessful attempts or the elapsed time has reached a programmable threshold.

公开(公告)号：US20190384528A1

公开(公告)日：2019-12-19

申请号：US16010940

申请日：2018-06-18

Applicant: Micron Technology, Inc.

Inventor： Nadav Grosz ,  David Aaron Palmer

IPC: G06F3/06

Abstract: Devices and techniques for an adjustable watchdog in a memory device are disclosed herein. A memory operation command is received at a first time with a memory device from a host. A reset signal is received, with the memory device from the host, at a second time following the first time. A time interval between the first time and the second time is measured. A delay interval for a timer in the memory device to reset the memory device independently of receiving a further reset signal from the host is established based on the measured time interval.

公开(公告)号：US12282431B2

公开(公告)日：2025-04-22

申请号：US17157303

申请日：2021-01-25

Applicant: Micron Technology, Inc.

Inventor： Nadav Grosz

IPC: G06F12/0866 ,  G06F3/06 ,  G06F12/02

Abstract: Devices and techniques are disclosed herein for implementing, in addition to a first cache, a second, persistent cache in a memory system coupled to a host. The memory system can include flash memory. In certain examples, the first cache and the second cache are configured to store mapping information. In some examples, the mapping information of the second persistent cache is determined by the host using a persistence flag of memory requests provided to the memory system.

公开(公告)号：US11934252B2

公开(公告)日：2024-03-19

申请号：US17648394

申请日：2022-01-19

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Nadav Grosz ,  Jonathan S. Parry

IPC: G06F1/32 ,  G06F1/3234 ,  G06F1/3287

CPC classification number: G06F1/3275 ,  G06F1/3287

Abstract: Methods, systems, and devices for shallow hibernate power state are described. A memory system may include a memory array and a controller. The memory system may transition from a first power state having a first current to a second power state having a second current less than the first current, where the first power state is associated with executing received commands and the second power state is associated with deactivating one or more components of the memory array. The memory system may initiate a timer after transitioning from the first power state to the second power state. The memory system may determine the timer satisfies a threshold and transition from the second power state to a third power state having a third current less than the second current based on the timer satisfying the threshold.

公开(公告)号：US11768629B2

公开(公告)日：2023-09-26

申请号：US17243321

申请日：2021-04-28

Applicant: Micron Technology, Inc.

Inventor： Luca Porzio ,  Nadav Grosz ,  Roberto Izzi ,  Jonathan S. Parry

IPC: G06F3/06 ,  G06F1/08

CPC classification number: G06F3/0659 ,  G06F1/08 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0673

Abstract: Methods, systems, and devices supporting techniques for memory system configuration using a queue refill time are described. A memory system may receive a command from a host system and may add the command to a command queue including a set of commands to be executed by the memory system. The memory system may determine a queue refill time of the command queue using measurements for at least one queue tag of the command queue and may adjust at least one resource of the command queue in response to the determined queue refill time. In some examples, the memory system may reallocate processing or memory resources previously allocated to the command queue, deactivate processing or memory resources previously allocated to the command queue, adjust a threshold queue depth for the command queue, or any combination thereof, among other options, based on the queue refill time.

公开(公告)号：US11693732B2

公开(公告)日：2023-07-04

申请号：US17014771

申请日：2020-09-08

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer ,  Nadav Grosz ,  Lance W. Dover ,  Yoav Weinberg

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/07 ,  G06F11/30 ,  G06F12/02 ,  G06F13/42 ,  G06F12/14

CPC classification number: G06F11/1068 ,  G06F11/0772 ,  G06F11/3037 ,  G06F12/0246 ,  G06F12/1408 ,  G06F13/4221 ,  G06F2212/7201

Abstract: A storage device includes a memory storage region and a controller having a processor. The processor retrieves user data from the memory storage region using a physical block address corresponding to a logical block address (LBA), in response to a read command. The retrieved user data includes a first hash received through a host interface in a prior host data transmission. The processor further performs error correction on the user data to generate error-corrected user data. The processor further causes a cryptographic engine to produce a second hash of the error-corrected user data. The first hash is compared to the second hash associated with the error-corrected user data to determine a match result. A notification is generated in response to the match result.

公开(公告)号：US11556481B2

公开(公告)日：2023-01-17

申请号：US16554937

申请日：2019-08-29

Applicant: Micron Technology, Inc.

Inventor： Nadav Grosz ,  Jonathan Scott Parry

IPC: G06F12/14 ,  G06F12/02

Abstract: Devices and techniques for efficient obfuscated logical-to-physical mapping are described herein. For example, activity corresponding to obfuscated regions of an L2P map for a memory device can be tracked. A record of discontinuity between the obfuscated regions and L2P mappings resulting from the activity can be updated. The obfuscated regions can be ordered based on a level of discontinuity from the record of discontinuity. When an idle period is identified, an obfuscated region from the obfuscated regions is selected and refreshed based on the ordering.

公开(公告)号：US11537327B2

公开(公告)日：2022-12-27

申请号：US17240723

申请日：2021-04-26

Applicant: Micron Technology, Inc.

Inventor： Nadav Grosz ,  David Aaron Palmer

IPC: G06F3/06 ,  G06F11/07 ,  G06F11/10 ,  G11C29/52

Abstract: Devices and techniques for an adjustable watchdog in a memory device are disclosed herein. A memory operation command is received at a first time with a memory device from a host. A reset signal is received, with the memory device from the host, at a second time following the first time. A time interval between the first time and the second time is measured. A delay interval for a timer in the memory device to reset the memory device independently of receiving a further reset signal from the host is established based on the measured time interval.

公开(公告)号：US20220327019A1

公开(公告)日：2022-10-13

申请号：US17851782

申请日：2022-06-28

Applicant: Micron Technology, Inc.

Inventor： Jonathan Scott Parry ,  Nadav Grosz ,  David Aaron Palmer ,  Christian M. Gyllenskog

IPC: G06F11/10 ,  G06F3/06 ,  G06F12/02

Abstract: Apparatus and methods are disclosed, including using a memory controller to monitor at least one parameter related to power level of a host processor of a host device, and dynamically adjusting at least one of a clock frequency and a voltage level of an error-correcting code (ECC) subsystem of the memory controller based on the at least one parameter to control power usage of the host device.

公开(公告)号：US20220214821A1

公开(公告)日：2022-07-07

申请号：US17702217

申请日：2022-03-23

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer ,  Sean L. Manion ,  Jonathan Scott Parry ,  Stephen Hanna ,  Qing Liang ,  Nadav Grosz ,  Chistian M. Gyllenskog ,  Kulachet Tanpairoj

IPC: G06F3/06 ,  G06F12/02

Abstract: Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.