公开(公告)号：US10938395B2

公开(公告)日：2021-03-02

申请号：US16809465

申请日：2020-03-04

Applicant: Micron Technology, Inc.

Inventor： Dan Shi ,  Tyler J. Gomm ,  Michael J. Allen

IPC: H03L7/08 ,  H03L7/081 ,  G11C11/4076 ,  H03K19/20 ,  G11C11/4074 ,  G11C11/408

Abstract: An electronic device including: a delay circuit configured to adjust a delay of an input for generating an output signal; and an input selection circuit coupled to the delay circuit, the input selection circuit configured to control a phase for a clock input based at least in part on a measurement of a delay corresponding to the delay circuit in generating the input.

公开(公告)号：US10770130B2

公开(公告)日：2020-09-08

申请号：US16557933

申请日：2019-08-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yasuo Satoh ,  Tyler J. Gomm

IPC: G11C11/4076 ,  H03K3/017 ,  H03K23/00 ,  H03M7/16 ,  G11C29/02 ,  H03K5/156 ,  G11C7/22 ,  H03K19/21

Abstract: Apparatuses and methods for maintaining a duty cycle error counter. An example apparatus may a duty cycle detect circuit configured to receive a clock signal and to detect a duty cycle error of the clock signal. The duty cycle detect error includes a counter configured to store a count value indicating the duty cycle error using Gray code. The counter is adjusted in response to detection of non-zero duty cycle error, and the counter is configured to convert the count value from Gray code to binary code as a binary count value. The duty cycle detect circuit is further configured to provide a duty cycle error signal based on the binary count value. The example apparatus further comprising a duty cycle correction circuit configured to adjust a duty cycle of the clock signal based on the duty cycle error signal.

公开(公告)号：US20200059237A1

公开(公告)日：2020-02-20

申请号：US16566703

申请日：2019-09-10

Applicant: Micron Technology, Inc.

Inventor： Dan Shi ,  Tyler J. Gomm ,  Michael J. Allen

IPC: H03L7/08 ,  G11C11/4076 ,  H03L7/081 ,  H03K19/20

Abstract: An electronic device including: a variable delay circuit configured to adjust a delay of a variable delay input for generating an output signal; a decision circuit coupled to the variable delay, the decision circuit configured to: generate a start signal for the variable delay circuit to begin measuring a coarse delay, generate a stop signal for the variable delay circuit to stop measuring the coarse delay, and generate an inversion-decision signal based at least in part on measuring the coarse delay; and an input selection circuit coupled to the variable delay circuit and the decision circuit, the input selection circuit configured to control a phase for a clock input based on the inversion-decision signal in generating the variable delay input.

公开(公告)号：US10454484B1

公开(公告)日：2019-10-22

申请号：US16103822

申请日：2018-08-14

Applicant: Micron Technology, Inc.

Inventor： Dan Shi ,  Tyler J. Gomm ,  Michael J. Allen

IPC: H03L7/08 ,  H03L7/081 ,  G11C11/4076 ,  H03K19/20 ,  G11C11/4074 ,  G11C11/408

Abstract: An electronic device including: a variable delay circuit configured to adjust a delay of a variable delay input for generating an output signal; a decision circuit coupled to the variable delay, the decision circuit configured to: generate a start signal for the variable delay circuit to begin measuring a coarse delay, generate a stop signal for the variable delay circuit to stop measuring the coarse delay, and generate an inversion-decision signal based at least in part on measuring the coarse delay; and an input selection circuit coupled to the variable delay circuit and the decision circuit, the input selection circuit configured to control a phase for a clock input based on the inversion-decision signal in generating the variable delay input.

公开(公告)号：US20190123748A1

公开(公告)日：2019-04-25

申请号：US16220489

申请日：2018-12-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tyler J. Gomm

IPC: H03K21/38

Abstract: Circuits, apparatuses, and methods are disclosed for frequency division. In one such example circuit, a frequency divider is configured to alternate between providing a common frequency clock signal as an output clock signal through a first circuit responsive to a reference clock signal and providing a reduced frequency clock signal as the output clock signal through a second circuit responsive to the reference clock signal. The first and second circuits share a shared circuit through which the output clock signal is provided. An enable circuit is configured to cause the frequency divider to alternate between providing the common frequency clock signal as the output clock signal through the first circuit and the reduced frequency clock signal as the output clock signal through the second circuit.

公开(公告)号：US09294105B2

公开(公告)日：2016-03-22

申请号：US14083875

申请日：2013-11-19

Applicant: Micron Technology, Inc.

Inventor： Tyler J. Gomm ,  Debra Bell

IPC: H03L7/08 ,  G11C7/22 ,  H03L7/081

CPC classification number: H03L7/0802 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0814

Abstract: A method and apparatus is provided for controlling a delay line for achieving power reduction. The device comprises a delay lock loop to provide an output signal based upon a phase difference between a reference signal and a feedback signal, said delay lock loop comprising at least one delay circuit comprising a plurality of logic gates configured to provide for substantially uniform degradation of a plurality of NAND gates in a static state.

公开(公告)号：US20140333357A1

公开(公告)日：2014-11-13

申请号：US14445924

申请日：2014-07-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Venkatraghavan Bringivijayaraghavan ,  Jason Brown ,  Tyler J. Gomm

IPC: H03L7/08 ,  H03K5/159

CPC classification number: H03L7/0802 ,  G11C7/04 ,  G11C7/222 ,  H03K5/159 ,  H03L7/08 ,  H03L7/0816

Abstract: Circuits, apparatuses, and methods are disclosed for delay models. In one such example circuit, a first delay model circuit is configured to provide a first output signal by modeling a delay of a signal through a path. A second delay model circuit is configured to provide a second output signal by modeling the delay of the signal through the path. A compare circuit is coupled to the first and second delay model circuits. The compare circuit is configured to compare a third signal from the first delay model circuit and a fourth signal from the second delay model circuit, and, in response provide an adjustment signal to adjust the delay of the second delay model circuit.

Abstract translation: 公开延迟模型的电路，装置和方法。 在一个这样的示例电路中，第一延迟模型电路被配置为通过对通过路径的信号的延迟进行建模来提供第一输出信号。 第二延迟模型电路被配置为通过对通过路径的信号的延迟进行建模来提供第二输出信号。 比较电路耦合到第一和第二延迟模型电路。 比较电路被配置为比较来自第一延迟模型电路的第三信号和来自第二延迟模型电路的第四信号，并且响应于提供调整信号以调整第二延迟模型电路的延迟。

公开(公告)号：US08502579B2

公开(公告)日：2013-08-06

申请号：US13734745

申请日：2013-01-04

Applicant: Micron Technology, Inc.

Inventor： Tyler J. Gomm

IPC: H03L7/06

CPC classification number: H03L7/0818 ,  H03K5/133 ,  H03K5/14 ,  H03L7/0814 ,  H03L7/089

Abstract: Locked loops, delay lines, delay circuits, and methods for delaying signals are disclosed. An example delay circuit includes a delay line including a plurality of delay stages, each delay stage having an input and further having a single inverting delay device, and also includes a two-phase exit tree coupled to the delay line and configured to provide first and second output clock signals responsive to clock signals from inputs of the delay stages of the plurality of delay stages. Another example delay circuit includes a delay line configured to provide a plurality of delayed clock signals, each of the delayed clock signals having a delay relative to a previous delayed clock signal equal to a delay of a single inverting delay device. The example delay circuit also includes a two-phase exit tree configured to provide first and second output clock signals responsive to the delayed clock signals.