公开(公告)号：US11843385B1

公开(公告)日：2023-12-12

申请号：US17857869

申请日：2022-07-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yasuo Satoh

IPC: H03K5/156 ,  H03K5/134 ,  G11C11/4076

CPC classification number: H03K5/1565 ,  G11C11/4076 ,  H03K5/134

Abstract: Disclosed herein is an apparatus that includes: a first input node supplied with a first clock signal; a first clock path configured to output a delayed first clock signal, the first clock path including first and second delay elements coupled in series; a second clock path configured to output additional delayed first clock signal, the second clock path including third and fourth delay elements coupled in series; a first mixer circuit configured to interpolate the delayed first clock signal and the additional delayed first clock signal to reproduce an adjusted clock signal as the first clock signal; and a control circuit configured to control delay amounts of the first, second, third, and fourth delay elements with first, second, third, and fourth codes different from one another.

公开(公告)号：US11646073B2

公开(公告)日：2023-05-09

申请号：US17720048

申请日：2022-04-13

Applicant: Micron Technology, Inc.

Inventor： Hyunui Lee ,  Takamasa Suzuki ,  Yasuo Satoh ,  Yuan He

IPC: G11C5/14 ,  G11C11/4074 ,  G11C11/4091 ,  G11C11/4063 ,  G11C11/4099 ,  H01L27/108 ,  G11C5/06

CPC classification number: G11C11/4074 ,  G11C11/4063 ,  G11C11/4091 ,  G11C11/4099 ,  H01L27/10802 ,  G11C5/063

Abstract: Some embodiments include an integrated assembly having a deck over a base, and having memory cells supported by the deck. Each of the memory cells includes a capacitive unit and a transistor. The individual capacitive units of the memory cells each have a storage node electrode, a plate electrode, and a capacitor dielectric material between the storage node electrode and the plate electrode. A reference-voltage-generator includes resistive units supported by the deck. The resistive units are similar to the memory cells but include interconnecting units in place of the capacitive units. The interconnecting units of some adjacent resistive units are shorted to one another.

公开(公告)号：US20220246193A1

公开(公告)日：2022-08-04

申请号：US17720048

申请日：2022-04-13

Applicant: Micron Technology, Inc.

Inventor： Hyunui Lee ,  Takamasa Suzuki ,  Yasuo Satoh ,  Yuan He

IPC: G11C11/4074 ,  G11C11/4091 ,  G11C11/4063 ,  G11C11/4099 ,  H01L27/108

Abstract: Some embodiments include an integrated assembly having a deck over a base, and having memory cells supported by the deck. Each of the memory cells includes a capacitive unit and a transistor. The individual capacitive units of the memory cells each have a storage node electrode, a plate electrode, and a capacitor dielectric material between the storage node electrode and the plate electrode. A reference-voltage-generator includes resistive units supported by the deck. The resistive units are similar to the memory cells but include interconnecting units in place of the capacitive units. The interconnecting units of some adjacent resistive units are shorted to one another.

公开(公告)号：US11282566B2

公开(公告)日：2022-03-22

申请号：US16743616

申请日：2020-01-15

Applicant: Micron Technology, Inc.

Inventor： Yasuo Satoh

IPC: G11C11/4076 ,  H03L7/081 ,  H03K5/14 ,  H03K5/131 ,  H03K5/00

Abstract: Apparatuses and methods for adjusting a phase mixer circuit are disclosed. An example method includes providing data values stored by a plurality of first registers and a plurality of second registers. The method includes: during a first mode of operation, receiving the data values by groups of first registers of the plurality of the first registers and holding the data values by the plurality of second registers; during a second mode of operation, inverting a data value by one first register of the plurality of first registers at a time and holding the data values by the plurality of second registers; and during a third mode of operation, either inverting the data value by one first register of the plurality of first registers while holding the data values by the plurality of second registers or inverting a data value by one second register of the plurality of second registers while holding the data values by the plurality of first registers.

公开(公告)号：US11237579B2

公开(公告)日：2022-02-01

申请号：US16987262

申请日：2020-08-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yuan He ,  Yasuo Satoh

IPC: G05F1/46 ,  G11C7/10 ,  G11C5/06 ,  H03K19/00

Abstract: In an example semiconductor device, the voltage/temperature conditions of the semiconductor device and associated calibration codes of multiple instances of ZQ calibrations are pre-stored in a register array. When a pre-stored voltage/temperature condition occurs again, ZQ calibration is not performed. Instead, the associated pre-stored calibration code is retrieved from the register array and provided to the IO circuit. When a voltage/temperature condition of the semiconductor device does not match any pre-stored voltage/temperature condition in the register array, a ZQ calibration is performed. When the ZQ calibration is performed, a register in the register array is selected according to an update policy and updated by the calibration code newly provided by the ZQ calibration along with the voltage/temperature condition at the time when the ZQ calibration is performed.

公开(公告)号：US20210358541A1

公开(公告)日：2021-11-18

申请号：US17362822

申请日：2021-06-29

Applicant: Micron Technology, Inc.

Inventor： Kazutaka Miyano ,  Yasuo Satoh ,  Kenji Mae

IPC: G11C11/406 ,  H03L7/081

Abstract: A semiconductor device may include a delay locked loop (DLL) control circuit coupled to an update trigger generator and a DLL update circuit. The DLL control circuit may receive an update trigger signal and an internal refresh signal and configured to activate the DLL update circuit responsive to an update trigger in the update trigger signal and deactivate the DLL update circuit responsive to an active internal refresh signal. The DLL update circuit may perform DLL update to one or more memory cell arrays when activated and not perform DLL update to the memory cell arrays when deactivated. The DLL control circuit may reactivate the DLL update circuit once the internal refresh signal becomes inactive. In other scenarios, once the DLL update circuit is deactivated, the DLL update circuit stays deactivated until the next update trigger in the update trigger signal.

公开(公告)号：US20210217457A1

公开(公告)日：2021-07-15

申请号：US16743616

申请日：2020-01-15

Applicant: Micron Technology, Inc.

Inventor： Yasuo Satoh

IPC: G11C11/4076 ,  H03L7/081 ,  H03K5/131 ,  H03K5/14 ,  H03K5/00

Abstract: Apparatuses and methods for adjusting a phase mixer circuit are disclosed. An example method includes providing data values stored by a plurality of first registers and a plurality of second registers. The method includes: during a first mode of operation, receiving the data values by groups of first registers of the plurality of the first registers and holding the data values by the plurality of second registers; during a second mode of operation, inverting a data value by one first register of the plurality of first registers at a time and holding the data values by the plurality of second registers; and during a third mode of operation, either inverting the data value by one first register of the plurality of first registers while holding the data values by the plurality of second registers or inverting a data value by one second register of the plurality of second registers while holding the data values by the plurality of first registers.

公开(公告)号：US11043941B2

公开(公告)日：2021-06-22

申请号：US15923860

申请日：2018-03-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yasuo Satoh

IPC: H03K5/135 ,  G11C19/28 ,  H03K5/00

Abstract: Apparatuses and methods for adjusting a phase mixer circuit are disclosed. An example apparatus includes a shift register that includes a plurality of registers coupled in series to one another. The plurality of registers are grouped into a first group of registers and a second group of registers. The first group of registers includes first and second registers. The second group of registers includes a third register. The first and second registers of the first group of registers are configured to receive in common an output of the third register of the second group of registers so that both the first and second registers store the output of the third register responsive to a shift clock.

公开(公告)号：US20210111706A1

公开(公告)日：2021-04-15

申请号：US17086792

申请日：2020-11-02

Applicant: Micron Technology, Inc.

Inventor： Yasuo Satoh ,  Hiroki Takahashi ,  Shuichi Tsukada ,  Yuan He

IPC: H03H11/54 ,  H03H11/28 ,  H03K19/00

Abstract: A memory device includes a terminal calibration circuit having at least one of a pull-down circuit or a pull-up circuit used in calibrating an impedance of a data bus termination. The memory device also includes a reference calibration circuit configured to generate a calibration current. The terminal calibration circuit can be configured to program an impedance of the least one of a pull-down circuit or a pull-up circuit based on the calibration current.

公开(公告)号：US10886898B1

公开(公告)日：2021-01-05

申请号：US16598964

申请日：2019-10-10

Applicant: Micron Technology, Inc.

Inventor： Yasuo Satoh ,  Hiroki Takahashi ,  Shuichi Tsukada ,  Yuan He

IPC: H03H11/54 ,  H03K19/00 ,  H03H11/28

Abstract: A memory device includes a terminal calibration circuit having at least one of a pull-down circuit or a pull-up circuit used in calibrating an impedance of a data bus termination. The memory device also includes a reference calibration circuit configured to generate a calibration current. The terminal calibration circuit can be configured to program an impedance of the least one of a pull-down circuit or a pull-up circuit based on the calibration current.