公开(公告)号：US20230043140A1

公开(公告)日：2023-02-09

申请号：US17963773

申请日：2022-10-11

Applicant: Micron Technology, Inc.

Inventor： Chulbum Kim ,  Mark A. Helm ,  Yoav Weinberg

IPC: G06F13/16 ,  G06F1/26

Abstract: Methods, systems, and devices for status check using chip enable pin are described. An apparatus may include a memory device, a pin coupled with the memory device, and a driver coupled with the pin and configured to bias the pin to a first a voltage or a second voltage based on a status of the memory device. The status may indicate, for example, whether the memory device is available to receive a command. The driver may bias the pin to a first voltage based on a first status of the memory device indicating that the memory device is busy. Additionally, or alternatively, the driver may bias the pin to a second voltage based on a second status of the memory device indicating that the memory device is available to receive the command. In some cases, the pin may be an example of a chip enable pin.

公开(公告)号：US11374592B2

公开(公告)日：2022-06-28

申请号：US16806826

申请日：2020-03-02

Applicant: Micron Technology, Inc.

Inventor： Eyal En Gad ,  Zhengang Chen ,  Sivagnanam Parthasarathy ,  Yoav Weinberg

IPC: H03M13/11 ,  H03M13/15 ,  H03M13/00 ,  G06F11/10

Abstract: A processing device in a memory system reads a sense word from a memory device and executes a plurality of parity check equations on corresponding subsets of the sense word to determine a plurality of parity check equation results. The processing device determines a syndrome for the sense word using the plurality of parity check equation results, determines whether the syndrome for the sense word satisfies a codeword criterion, and responsive to the syndrome for the sense word not satisfying the codeword criterion, performs an iterative low density parity check (LDPC) correction process, wherein at least one criterion of the iterative LDPC correction process is adjusted after a threshold number of iterations is performed.

公开(公告)号：US11188473B1

公开(公告)日：2021-11-30

申请号：US16949512

申请日：2020-10-30

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee ,  Yoav Weinberg

IPC: G06F12/00 ,  G06F12/0882 ,  G06F12/0817 ,  G06F9/30 ,  G06F12/0891

Abstract: A memory device includes a page cache comprising a cache register, a memory array configured with a plurality of memory planes, and control logic, operatively coupled with the memory array. The control logic receives, from a requestor, a first cache read command requesting first data from the memory array spread across the plurality of memory planes, and returns, to the requestor, data associated with a first subset of the plurality of memory planes and pertaining to a previous read command, while concurrently copying data associated with a second subset of the plurality of memory planes and pertaining to the previous read command into the cache register. The control logic further receives, from the requestor, a cache release command, and returns, to the requestor, the data associated with the second subset of the plurality of memory planes and pertaining to the previous read command, while concurrently copying data associated with the first subset of the plurality of memory planes and pertaining to the first cache read command into the cache register.

公开(公告)号：US20210273653A1

公开(公告)日：2021-09-02

申请号：US16806826

申请日：2020-03-02

Applicant: Micron Technology, Inc.

Inventor： Eyal En Gad ,  Zhengang Chen ,  Sivagnanam Parthasarathy ,  Yoav Weinberg

IPC: H03M13/11 ,  G06F11/10

Abstract: A processing device in a memory system reads a sense word from a memory device and executes a plurality of parity check equations on corresponding subsets of the sense word to determine a plurality of parity check equation results. The processing device determines a syndrome for the sense word using the plurality of parity check equation results, determines whether the syndrome for the sense word satisfies a codeword criterion, and responsive to the syndrome for the sense word not satisfying the codeword criterion, performs an iterative low density parity check (LDPC) correction process, wherein at least one criterion of the iterative LDPC correction process is adjusted after a threshold number of iterations is performed.

公开(公告)号：US20210200631A1

公开(公告)日：2021-07-01

申请号：US17014771

申请日：2020-09-08

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer ,  Nadav Grosz ,  Lance W. Dover ,  Yoav Weinberg

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/30 ,  G06F12/14 ,  G06F12/02 ,  G06F13/42

Abstract: A storage device includes a memory storage region and a controller having a processor. The processor retrieves user data from the memory storage region using a physical block address corresponding to a logical block address (LBA), in response to a read command. The retrieved user data includes a first hash received through a host interface in a prior host data transmission. The processor further performs error correction on the user data to generate error-corrected user data. The processor further causes a cryptographic engine to produce a second hash of the error-corrected user data. The first hash is compared to the second hash associated with the error-corrected user data to determine a match result. A notification is generated in response to the match result.

公开(公告)号：US20250094364A1

公开(公告)日：2025-03-20

申请号：US18967215

申请日：2024-12-03

Applicant: Micron Technology, Inc.

Inventor： Chulbum Kim ,  Mark A. Helm ,  Yoav Weinberg

IPC: G06F13/16 ,  G06F1/26

Abstract: Methods, systems, and devices for status check using chip enable pin are described. An apparatus may include a memory device, a pin coupled with the memory device, and a driver coupled with the pin and configured to bias the pin to a first a voltage or a second voltage based on a status of the memory device. The status may indicate, for example, whether the memory device is available to receive a command. The driver may bias the pin to a first voltage based on a first status of the memory device indicating that the memory device is busy. Additionally, or alternatively, the driver may bias the pin to a second voltage based on a second status of the memory device indicating that the memory device is available to receive the command. In some cases, the pin may be an example of a chip enable pin.

公开(公告)号：US20250036526A1

公开(公告)日：2025-01-30

申请号：US18791729

申请日：2024-08-01

Applicant: Micron Technology, Inc.

Inventor： Chandrakanth Rapalli ,  Yoav Weinberg ,  Tal Sharifie

IPC: G06F11/10

Abstract: Methods, systems, and devices for command and data path error protection are described. In some examples, a memory system may receive data units from a host device. The data units may include respective sets of parity bits, and the memory system may perform an error detection operation on the data units. A first controller of the memory system may generate a protocol unit using data (e.g., a subset of data) from the data units. The protocol unit may include a set of parity bits (e.g., a different set of parity bits), and a second controller of the memory system may perform an error detection operation on the protocol unit. The second controller of the memory system may generate a data storage unit using data (e.g., a subset of data) from the protocol unit, and may store the data unit and another set of parity bits to a memory device.

公开(公告)号：US12169461B2

公开(公告)日：2024-12-17

申请号：US17963773

申请日：2022-10-11

Applicant: Micron Technology, Inc.

Inventor： Chulbum Kim ,  Mark A. Helm ,  Yoav Weinberg

IPC: G06F13/14 ,  G06F1/26 ,  G06F13/16

Abstract: Methods, systems, and devices for status check using chip enable pin are described. An apparatus may include a memory device, a pin coupled with the memory device, and a driver coupled with the pin and configured to bias the pin to a first a voltage or a second voltage based on a status of the memory device. The status may indicate, for example, whether the memory device is available to receive a command. The driver may bias the pin to a first voltage based on a first status of the memory device indicating that the memory device is busy. Additionally, or alternatively, the driver may bias the pin to a second voltage based on a second status of the memory device indicating that the memory device is available to receive the command. In some cases, the pin may be an example of a chip enable pin.

公开(公告)号：US12159667B2

公开(公告)日：2024-12-03

申请号：US17831414

申请日：2022-06-02

Applicant: Micron Technology, Inc.

Inventor： Neil Petrie ,  Yoav Weinberg

IPC: G11C13/00

Abstract: An example apparatus include an array of memory cells. The example apparatus includes a memory controller coupled to the array. The memory controller can include an internal reference resistor. The memory controller can be configured to monitor memory characteristics for the array and the memory controller. The memory controller can be configured to trim the internal reference resistor to result in a target resistance value based on the memory characteristics.

公开(公告)号：US20240396571A1

公开(公告)日：2024-11-28

申请号：US18672533

申请日：2024-05-23

Applicant: Micron Technology, Inc.

Inventor： Chandrakanth Rapalli ,  Yoav Weinberg ,  Tal Sharifie

IPC: H03M13/09 ,  G06F11/10 ,  H03M13/00

Abstract: Methods, systems, and devices for error protection for managed memory devices are described. In some examples, a memory system may receive data units from a host device. The data units may include respective sets of parity bits, and the memory system may perform an error detection operation on the data units. A first controller of the memory system may generate a protocol unit using data (e.g., a subset of data) from the data units. The protocol unit may include a set of parity bits (e.g., a different set of parity bits), and a second controller of the memory system may perform an error detection operation on the protocol unit. The second controller of the memory system may generate a data storage unit using data (e.g., a subset of data) from the protocol unit, and may store the data unit and another set of parity bits to a memory device.