-
公开(公告)号：US20230015706A1
公开(公告)日：2023-01-19
申请号：US17953269
申请日：2022-09-26
发明人： Tingjun Xie , Zhengang Chen , Zhenlei Shen
IPC分类号： G06F9/50 , G11C11/4074 , G06F12/06
摘要： A system can include a memory component and a processing device. The processing device can receive an indication to remove a group of memory cells of a memory sub-system from a logical address space that is used to access the memory sub-system. The processing device can, responsive to receiving the indication, remove the group of memory cells of the memory sub-system from the logical address space. The processing device can program the group of memory cells that have been removed from the logical address space with a voltage state.
-
42.发明授权公开(公告)号：US11374592B2
公开(公告)日：2022-06-28
申请号：US16806826
申请日：2020-03-02
摘要： A processing device in a memory system reads a sense word from a memory device and executes a plurality of parity check equations on corresponding subsets of the sense word to determine a plurality of parity check equation results. The processing device determines a syndrome for the sense word using the plurality of parity check equation results, determines whether the syndrome for the sense word satisfies a codeword criterion, and responsive to the syndrome for the sense word not satisfying the codeword criterion, performs an iterative low density parity check (LDPC) correction process, wherein at least one criterion of the iterative LDPC correction process is adjusted after a threshold number of iterations is performed.
-
公开(公告)号：US20220171703A1
公开(公告)日：2022-06-02
申请号：US17676595
申请日：2022-02-21
发明人： Zhengang Chen , Jianmin Huang
IPC分类号： G06F12/02 , G06F12/0804 , G06F12/0817 , G06F9/30 , G06F11/10 , G06F12/14
摘要： Disclosed in some examples are methods, systems, devices, and machine-readable mediums that provide for techniques for scrambling and/or updating meta-data that enable an efficient internal copyback operation. In some examples, in order to update the meta-data, the meta-data and host-data are separated and the only the meta-data is sent to the controller to be updated during a modified internal copyback operation. The host-data is not transmitted to the controller. While sending the meta-data utilizes resources of the communication link between the memory dies and the controller, it uses much fewer resources than if the host-data were also transmitted.
-
公开(公告)号：US20210304826A1
公开(公告)日：2021-09-30
申请号：US17347570
申请日：2021-06-14
IPC分类号： G11C16/34 , G11C29/52 , G06F11/10 , G11C16/26 , G11C29/42 , G06F11/07 , G06F11/14 , G11C29/44
摘要： Described herein are embodiments related to defect detection in memory components of memory systems with time-varying bit error rate. A processing device determines that a bit error rate (BER) corresponding to a read operation to read a unit of data in a memory component satisfies a threshold criterion, determines a write-to-read (W2R) delay for the read operation, wherein the W2R delay comprises a difference between a time of the read operation and a write timestamp indicating when the unit of data was written to the memory component, and determines whether the W2R delay is within a W2R delay range corresponding to an initial read voltage level used by the read operation to read the unit of data. The processing device initiates a defect detection operation responsive to the W2R delay being within the W2R delay range, the defect detection operation to detect time-varying defects in the memory component.
-
公开(公告)号：US20210295900A1
公开(公告)日：2021-09-23
申请号：US17339047
申请日：2021-06-04
IPC分类号： G11C11/406 , G11C11/16
摘要： A media management operation can be performed at a memory sub-system at a current frequency. An operating characteristic associated with the memory sub-system can be identified. The operating characteristic can reflect at least one of a write count, a bit error rate, or a read-retry trigger rate. A determination can be made as to whether the identified operating characteristic satisfies an operating characteristic criterion. In response to determining that the operating characteristic satisfies the characteristic criterion, the media management operation can be performed at a different frequency relative to the current frequency.
-
46.发明申请公开(公告)号：US20210273653A1
公开(公告)日：2021-09-02
申请号：US16806826
申请日：2020-03-02
摘要： A processing device in a memory system reads a sense word from a memory device and executes a plurality of parity check equations on corresponding subsets of the sense word to determine a plurality of parity check equation results. The processing device determines a syndrome for the sense word using the plurality of parity check equation results, determines whether the syndrome for the sense word satisfies a codeword criterion, and responsive to the syndrome for the sense word not satisfying the codeword criterion, performs an iterative low density parity check (LDPC) correction process, wherein at least one criterion of the iterative LDPC correction process is adjusted after a threshold number of iterations is performed.
-
公开(公告)号：US20210011769A1
公开(公告)日：2021-01-14
申请号：US16510426
申请日：2019-07-12
发明人： Tingjun Xie , Zhengang Chen , Zhenlei Shen
IPC分类号： G06F9/50 , G06F12/06 , G11C11/4074
摘要： An indication that an allocation unit of a memory sub-system has become unmapped can be received. In response to receiving the indication that the allocation unit of the memory sub-system has become unmapped, the allocation unit can be programmed with a data pattern. Data to be written to the unmapped allocation unit can be received. A write operation can be performed to program the received data at the unmapped allocation unit by using a read voltage that is based on the data pattern.
-
公开(公告)号：US10892029B1
公开(公告)日：2021-01-12
申请号：US16510454
申请日：2019-07-12
发明人： Tingjun Xie , Zhengang Chen
摘要： A processing device in a memory system identifies a first range of a plurality of write-to-read delay ranges for the memory component, wherein the first range represents a plurality of write-to-read delay times and has an associated read voltage level used to perform a read operation on a segment of the memory component having a write-to-read delay time that falls within the first range. The processing device further identifies a first set of the plurality of write-to-read delay times at a first end of the first range and determines a first directional error rate for the memory component corresponding to the first set of the plurality of write-to-read delay times and a second directional error rate for the memory component corresponding to the first set of the plurality of write-to-read delay times. The processing device determines whether a correspondence between the first directional error rate and the second directional error rate satisfies a first threshold criterion and, responsive to the correspondence between the first directional error rate and the second directional error rate not satisfying the first threshold criterion, modifies the read voltage level associated with the first range.
-
公开(公告)号：US10761754B2
公开(公告)日：2020-09-01
申请号：US16057537
申请日：2018-08-07
发明人： Zhenlei E. Shen , Zhengang Chen , Tingjun Xie , Jiangli Zhu
摘要： Data can be received at a memory sub-system. A characteristic of the memory sub-system can be identified. A read voltage level can be determined based on the characteristic of the memory sub-system. A read operation can be performed at the memory sub-system based on the read voltage level to retrieve stored data. The received data can be stored at the memory sub-system based on the stored data that was retrieved from the read operation that is based on the read voltage level.
-
公开(公告)号：US20200185045A1
公开(公告)日：2020-06-11
申请号：US16215267
申请日：2018-12-10
IPC分类号： G11C16/34 , G11C29/52 , G06F11/10 , G11C16/26 , G11C29/44 , G11C29/42 , G06F11/07 , G06F11/14
摘要： Described herein are embodiments related to defect detection in memory components of memory systems with time-varying bit error rate. A processing device performs an error recovery flow (ERF) to recover a unit of data comprising data and a write timestamp indicating when the unit of data was written. The processing device determines whether to perform a defect detection operation to detect a defect in the memory component using a bit error rate (BER), corresponding to the read operation, and the write timestamp in the unit of data. The processing device initiates the defect detection operation responsive to the BER condition not being expected for the calculated W2R (based on the write timestamp). The processing device can use an ERF condition and the write timestamp to determine whether to perform the defect detection operation. The processing device initiates the defect detection operation responsive to the ERF condition not being expected the calculated W2R (based on the write timestamp).
-
-
-
-
-
-
-
-
-
搜索结果
65 条记录 (耗时 0.027 秒)