公开(公告)号：US20180130513A1

公开(公告)日：2018-05-10

申请号：US15858837

申请日：2017-12-29

Applicant: Micron Technology, Inc.

Inventor： Christopher John Kawamura

IPC: G11C11/22 ,  G11C11/56

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/2275 ,  G11C11/5657

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. In some examples, multi-level accessing, sensing, and other operations for ferroelectric memory may be based on sensing multiple charges, including a first charge associated with a dielectric of the memory cell and a second charge associated with a polarization of the memory cell. In some cases, multi-level accessing, sensing, and other operations may be based on transferring a first charge associated with a dielectric of the memory cell to a sense amplifier, isolating the sense amplifier, activating the sense amplifier, transferring a second charge associated with a polarization of the memory cell to the sense amplifier, and activating the sense amplifier a second time.

公开(公告)号：US09899073B2

公开(公告)日：2018-02-20

申请号：US15194178

申请日：2016-06-27

Applicant: Micron Technology, Inc.

Inventor： Christopher John Kawamura

IPC: G11C11/22 ,  G11C11/56

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/2275 ,  G11C11/5657

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. In some examples, multi-level accessing, sensing, and other operations for ferroelectric memory may be based on sensing multiple charges, including a first charge associated with a dielectric of the memory cell and a second charge associated with a polarization of the memory cell. In some cases, multi-level accessing, sensing, and other operations may be based on transferring a first charge associated with a dielectric of the memory cell to a sense amplifier, isolating the sense amplifier, activating the sense amplifier, transferring a second charge associated with a polarization of the memory cell to the sense amplifier, and activating the sense amplifier a second time.

公开(公告)号：US20170365322A1

公开(公告)日：2017-12-21

申请号：US15692994

申请日：2017-08-31

Applicant: Micron Technology, Inc.

Inventor： Christopher John Kawamura ,  Scott James Derner

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C7/14 ,  G11C11/221 ,  G11C11/2293

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A portion of charge of a memory cell may be captured and, for example, stored using a capacitor or intrinsic capacitance of the memory array that includes the memory cell. The memory cell may be recharged (e.g., re-written). The memory cell may then be read, and a voltage of the memory cell may be compared to a voltage resulting from the captured charge. A logic state of the memory cell may be determined based at least in part on the voltage comparison.

公开(公告)号：US09792973B2

公开(公告)日：2017-10-17

申请号：US15073989

申请日：2016-03-18

Applicant: Micron Technology, Inc.

Inventor： Christopher John Kawamura ,  Scott James Derner

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2275

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory device may maintain a digit line voltage at a ground reference for a duration associated with biasing a ferroelectric capacitor of a memory cell. For example, a digit line that is in electronic communication with a ferroelectric capacitor may be virtually grounded while a voltage is applied to a plate of the ferroelectric capacitor, and the ferroelectric capacitor may be isolated from the virtual ground after a threshold associated with applying the voltage to the plate is reached. A switching component (e.g., a transistor) that is in electronic communication with the digit line and virtual ground may be activated to virtually ground the digit line and deactivated to isolate the digit line from virtual ground.

公开(公告)号：US20170256300A1

公开(公告)日：2017-09-07

申请号：US15057914

申请日：2016-03-01

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati ,  Scott James Derner ,  Umberto Di Vincenzo ,  Christopher John Kawamura ,  Eric S. Carman

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2293

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ground reference scheme may be employed in a digit line voltage sensing operation. A positive voltage may be applied to a memory cell; and after a voltage of the digit line of the cell has reached a threshold, a negative voltage may be applied to cause the digit line voltages to center around ground before a read operation. In another example, a first voltage may be applied to a memory cell and then a second voltage that is equal to an inverse of the first voltage may be applied to a reference capacitor that is in electronic communication with a digit line of the memory cell to cause the digit line voltages to center around ground before a read operation.

公开(公告)号：US09734886B1

公开(公告)日：2017-08-15

申请号：US15012566

申请日：2016-02-01

Applicant: Micron Technology, Inc.

Inventor： Scott James Derner ,  Christopher John Kawamura

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2255 ,  G11C11/2297

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be initialized to a first state and a second ferroelectric memory cell may be initialized to a different state. Each state may have a corresponding digit line voltage. The digit lines of the first and second ferroelectric memory cells may be connected so that charge-sharing occurs between the two digit lines. The voltage resulting from the charge-sharing between the two digit lines may be used by other components as a reference voltage.

公开(公告)号：US20250130908A1

公开(公告)日：2025-04-24

申请号：US18937428

申请日：2024-11-05

Applicant: Micron Technology, Inc.

Inventor： Christopher John Kawamura ,  Scott James Derner ,  Charles L. Ingalls

IPC: G06F11/20 ,  G06F11/10 ,  G06F11/14 ,  G11C11/22 ,  G11C29/12 ,  G11C29/36 ,  G11C29/42 ,  G11C29/44 ,  G11C29/52

Abstract: Methods, systems, and apparatuses for storing operational information related to operation of a non-volatile array are described. For example, the operational information may be stored in a in a subarray of a memory array for use in analyzing errors in the operation of memory array. In some examples, an array driver may be located between a command decoder and a memory array. The array driver may receive a signal pattern used to execute an access instruction for accessing non-volatile memory cells of a memory array and may access the first set of non-volatile memory cells according to the signal pattern. The array driver may also store the access instruction (e.g., the binary representation of the access instruction) at a non-volatile subarray of the memory array.

公开(公告)号：US20240144983A1

公开(公告)日：2024-05-02

申请号：US17975300

申请日：2022-10-27

Applicant: Micron Technology, Inc.

Inventor： Luoqi Li ,  Huy Thanh Vo ,  Christopher John Kawamura

IPC: G11C7/10 ,  G11C7/06 ,  G11C7/12

CPC classification number: G11C7/1063 ,  G11C7/06 ,  G11C7/1069 ,  G11C7/12

Abstract: An apparatus may include a sense amplifier with a single column select transistor, a local input/output line selectively couplable to a first bit line through the column select transistor, and a read/write gap comprising at least a first transistor and a second transistor. The first transistor may be couplable to a read select signal and a complimentary local input/output line and the second transistor is couplable to the complimentary local input/output line and a global input/output line.

公开(公告)号：US11948622B2

公开(公告)日：2024-04-02

申请号：US17659405

申请日：2022-04-15

Applicant: Micron Technology, Inc.

Inventor： Martin Brox ,  C. Omar Benitez ,  Johnathan L. Gossi ,  Christopher John Kawamura

IPC: G11C11/40 ,  G11C5/14 ,  G11C11/22 ,  G11C11/408 ,  G11C11/4094

CPC classification number: G11C11/4085 ,  G11C5/14 ,  G11C11/2259 ,  G11C11/4094 ,  G11C11/221

Abstract: Methods, systems, and devices for techniques for generating access line voltages are described. A system may use a first voltage supply and a second voltage supply that is configured to supply a lower voltage than the first voltage supply. The system may activate a first circuit to couple a node with the first voltage supply so that a first voltage develops on the node from the first voltage supply. The system may activate a second circuit to couple the node with the second voltage supply so that a second voltage that is lower than the first voltage develops on the node from the second voltage supply.

公开(公告)号：US20210335409A1

公开(公告)日：2021-10-28

申请号：US17318721

申请日：2021-05-12

Applicant: Micron Technology, Inc.

Inventor： Christopher John Kawamura

IPC: G11C11/22 ,  G11C11/56

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. In some examples, multi-level accessing, sensing, and other operations for ferroelectric memory may be based on sensing multiple charges, including a first charge associated with a dielectric of the memory cell and a second charge associated with a polarization of the memory cell. In some cases, multi-level accessing, sensing, and other operations may be based on transferring a first charge associated with a dielectric of the memory cell to a sense amplifier, isolating the sense amplifier, activating the sense amplifier, transferring a second charge associated with a polarization of the memory cell to the sense amplifier, and activating the sense amplifier a second time.