公开(公告)号：US11740795B2

公开(公告)日：2023-08-29

申请号：US17721160

申请日：2022-04-14

Applicant: Micron Technology, Inc.

Inventor： Suryanarayana B. Tatapudi ,  John David Porter ,  Jaeil Kim ,  Mijo Kim

IPC: G06F3/06 ,  G06F13/16 ,  G11C7/10

CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0676 ,  G06F3/0679 ,  G06F13/1668 ,  G11C7/10 ,  G06F2213/16

Abstract: Techniques for configurable link interfaces for a memory device are described. In some examples, memory devices may require periodic link training to support data transfer with a host device at relatively fast rates. However, in some managed memory applications, memory dies of a memory device may have integrated controllers that do not support such link training, and accordingly may not support some clock rates or data rates. To support data transfers between a host device and a memory device at relatively fast clock rates or data rates without link training, a memory die may be fabricated with a configurable link interface that can support different mappings between components and operation according to different clock rates or data rates. In some examples, a memory die may be fabricated in a manner that supports configurable mappings between an array and a data channel interface that are operable according to different multiplexing and serialization.

公开(公告)号：US20220261027A1

公开(公告)日：2022-08-18

申请号：US17666124

申请日：2022-02-07

Applicant: Micron Technology, Inc.

Inventor： Anupriya Chakraborty ,  John David Porter ,  Alan John Wilson

IPC: G05F3/20

Abstract: Techniques for providing temperature trim codes to multiple reference circuits of an integrated circuit are provided. In an example, a string of primary latch circuits can provide a set of pre-defined temperature trim codes to a multiplexer in response to a token of a series of tokens. The multiplexer can provide two trim of the trim codes to an interpolator based on a temperature reading of the integrated circuit. The interpolator can provide an interpolated trim code and the trim code can be distributed to a reference circuit based on the token.

公开(公告)号：US20220101891A1

公开(公告)日：2022-03-31

申请号：US17546026

申请日：2021-12-08

Applicant: Micron Technology, Inc.

Inventor： John David Porter ,  Suryanarayana B. Tatapudi

IPC: G11C7/06 ,  G11C5/14

Abstract: Embodiments relate to improving the biasing of active electronic components such as, for example, sense amplifiers. Embodiments include an adjustable bias signal generator that receives a reference signal as an input and generates a corresponding bias signal as an output. The adjustable bias signal generator may comprise a voltage driver and capacitor divider circuitry. In some embodiments, the capacitor divider circuitry is configurable by selecting specific capacitor dividers using a digital code. In other embodiments, the voltage driver is adjustable by applying different trim settings to tune the output of the voltage driver. The voltage driver may be temperature compensated by multiplexing different trim settings that correspond to different temperatures.

公开(公告)号：US11232819B1

公开(公告)日：2022-01-25

申请号：US16934213

申请日：2020-07-21

Applicant: Micron Technology, Inc.

Inventor： John David Porter ,  Suryanarayana B. Tatapudi

IPC: G11C16/06 ,  G11C7/06 ,  G11C5/14

Abstract: Embodiments relate to improving the biasing of active electronic components such as, for example, sense amplifiers. Embodiments include an adjustable bias signal generator that receives a reference signal as an input and generates a corresponding bias signal as an output. The adjustable bias signal generator may comprise a voltage driver and capacitor divider circuitry. In some embodiments, the capacitor divider circuitry is configurable by selecting specific capacitor dividers using a digital code. In other embodiments, the voltage driver is adjustable by applying different trim settings to tune the output of the voltage driver. The voltage driver may be temperature compensated by multiplexing different trim settings that correspond to different temperatures.

公开(公告)号：US20220011934A1

公开(公告)日：2022-01-13

申请号：US16925773

申请日：2020-07-10

Applicant: Micron Technology, Inc.

Inventor： Suryanarayana B. Tatapudi ,  John David Porter ,  Jaeil Kim ,  Mijo Kim

IPC: G06F3/06 ,  G06F13/16

Abstract: Techniques for configurable link interfaces for a memory device are described. In some examples, memory devices may require periodic link training to support data transfer with a host device at relatively fast rates. However, in some managed memory applications, memory dies of a memory device may have integrated controllers that do not support such link training, and accordingly may not support some clock rates or data rates. To support data transfers between a host device and a memory device at relatively fast clock rates or data rates without link training, a memory die may be fabricated with a configurable link interface that can support different mappings between components and operation according to different clock rates or data rates. In some examples, a memory die may be fabricated in a manner that supports configurable mappings between an array and a data channel interface that are operable according to different multiplexing and serialization.

公开(公告)号：US20210328601A1

公开(公告)日：2021-10-21

申请号：US17307641

申请日：2021-05-04

Applicant: Micron Technology, Inc.

Inventor： John David Porter

IPC: H03M13/29 ,  G11C29/52 ,  G06F11/10

Abstract: Methods, systems, and devices for error correction on a memory device are described. Examples may include a memory die having an array of memory cells including a plurality of banks. The memory die may further include a first error correcting code (ECC) circuit coupled with a first bank of memory cells, where the first ECC circuit is configured to perform operations associated with a first access operation (e.g., write operation) of the first bank of memory cells. The memory die may further include a second ECC circuit coupled with the first bank of memory cells, where the second ECC circuit is configured to perform ECC operations associated with a second access operation (e.g., read operation) of the first bank. In some cases, the first ECC circuit may be located under the footprint of the array and the second ECC circuit may be located outside the footprint of the array.

公开(公告)号：US09653143B2

公开(公告)日：2017-05-16

申请号：US15170785

申请日：2016-06-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： John David Porter ,  Gi-Hong Kim

IPC: G11C7/00 ,  G11C11/406 ,  G11C8/08 ,  G11C8/10 ,  G11C11/408 ,  G11C5/14 ,  G11C11/402

CPC classification number: G11C11/40615 ,  G11C5/147 ,  G11C8/08 ,  G11C8/10 ,  G11C11/402 ,  G11C11/406 ,  G11C11/4085 ,  G11C2211/4065 ,  G11C2211/4067

Abstract: Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits. Each memory section control circuit is coupled to a respective one of the plurality of memory sections and includes a plurality of access line drivers, each of which includes a plurality of transistors having common coupled gates. During an operation of the apparatus a first voltage is provided to the commonly coupled gates of the transistors of at least some of the access line drivers of the memory section control circuit coupled to an active memory section and a second voltage is provided to the commonly coupled gates of the transistors of the access line drivers of the memory section control circuit coupled to an inactive memory section control circuit, wherein the first voltage is greater than the second voltage.

公开(公告)号：US20140078847A1

公开(公告)日：2014-03-20

申请号：US14084417

申请日：2013-11-19

Applicant: Micron Technology, Inc.

Inventor： John David Porter ,  Gi-Hong Kim

IPC: G11C5/14 ,  G11C11/402

CPC classification number: G11C11/40615 ,  G11C5/147 ,  G11C8/08 ,  G11C8/10 ,  G11C11/402 ,  G11C11/406 ,  G11C11/4085 ,  G11C2211/4065 ,  G11C2211/4067

Abstract: Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits. Each memory section control circuit is coupled to a respective one of the plurality of memory sections and includes a plurality of access line drivers, each of which includes a plurality of transistors having common coupled gates. During an operation of the apparatus a first voltage is provided to the commonly coupled gates of the transistors of at least some of the access line drivers of the memory section control circuit coupled to an active memory section an and a second voltage is provided to the commonly coupled gates of the transistors of the access line drivers of the memory section control circuit coupled to an inactive memory section control circuit, wherein the first voltage is greater than the second voltage.

Abstract translation: 公开了设备，存储器部分控制电路和刷新存储器的方法。 示例性设备包括多个存储器部分和多个存储器部分控制电路。 每个存储器部分控制电路耦合到多个存储器部分中的相应一个，并且包括多个存取线驱动器，每个存取线驱动器包括具有公共耦合栅极的多个晶体管。 在装置的操作期间，第一电压被提供给耦合到有源存储器部分a的存储器部分控制电路的至少一些存取线驱动器的晶体管的共同耦合的栅极，并且第二电压被提供给共同的 存储器部分控制电路的存取线路驱动器的晶体管的耦合到非活动存储器部分控制电路的耦合栅极，其中第一电压大于第二电压。