公开(公告)号：US11908913B2

公开(公告)日：2024-02-20

申请号：US17661187

申请日：2022-04-28

Applicant: Micron Technology, Inc.

Inventor： Durai Vishak Nirmal Ramaswamy ,  Ramanathan Gandhi ,  Scott E. Sills

IPC: H01L29/45 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H10B12/00

CPC classification number: H01L29/45 ,  H01L29/42356 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78642 ,  H01L29/78693 ,  H01L29/7827 ,  H10B12/05 ,  H10B12/30

Abstract: A semiconductor device is disclosed. The semiconductor device includes a transistor including a source contact, a drain contact, and a channel region including an oxide semiconductor material as the channel material. At least one of the drain contact or the source contact includes a conductive material, such as ruthenium, to reduce the Schottky effects at the interface with the channel material.

公开(公告)号：US11658246B2

公开(公告)日：2023-05-23

申请号：US16596370

申请日：2019-10-08

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Ramanathan Gandhi ,  Yi Fang Lee ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy ,  Scott E. Sills

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/45 ,  H01L29/417 ,  H01L29/66 ,  H01L21/02 ,  H01L21/441 ,  H01L29/78

CPC classification number: H01L29/78642 ,  H01L21/02178 ,  H01L21/02565 ,  H01L21/441 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/7827 ,  H01L29/7869 ,  H01L29/78618 ,  H01L29/78696

Abstract: A device comprises a vertical transistor. The vertical transistor comprises a pillar structure, at least one gate electrode, and a dielectric material. The pillar structure comprises a source region, a drain region, and a channel region. The source region and the drain region each individually comprise at least one electrically conductive material configured to inhibit hydrogen permeation therethrough. The channel region comprises a semiconductive material vertically between the source region and the drain region. The at least one gate electrode laterally neighbors the channel region of the semiconductive structure. The dielectric material is laterally between the semiconductive structure and the at least one gate electrode. Additional devices, and related electronic systems and methods are also disclosed.

公开(公告)号：US20230018127A1

公开(公告)日：2023-01-19

申请号：US17379338

申请日：2021-07-19

Applicant: Micron Technology, Inc.

Inventor： Ramanathan Gandhi ,  Sock Mui Poh ,  Dmitry Mikulik ,  Dae Hong Eom ,  Moonhyeong Han ,  Aireus O. Christensen ,  Chandrasekaran Venkatasubramanian

IPC: H01L27/1157 ,  H01L27/11565 ,  H01L25/065

Abstract: A microelectronic device includes a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. At least one pillar extends through the stack structure. The at least one pillar includes at least one insulative material and a channel structure horizontally surrounding the at least one insulative material. The at least one channel structure comprises sub-regions of semiconductor material. At least one of the sub-regions exhibits a different microstructure than at least one other of the sub-regions. Additional microelectronic devices are also disclosed, as are related methods and electronic systems.

公开(公告)号：US20220416088A1

公开(公告)日：2022-12-29

申请号：US17822420

申请日：2022-08-25

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills ,  Ramanathan Gandhi ,  Durai Vishak Nirmal Ramaswamy

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/24

Abstract: A method of forming a device comprises forming dielectric structures over other dielectric structures overlying conductive contact structures, the dielectric structures separated from one another by trenches and laterally extending orthogonal to the other dielectric structures and the conductive contact structures. Conductive gate structures are formed on exposed side surfaces of the dielectric structures within the trenches. Dielectric oxide structures are formed on exposed side surfaces of the conductive gate structures within the trenches. Exposed portions of the other dielectric structures are removed to form isolation structures. Semiconductive pillars are formed on exposed side surfaces of the dielectric oxide structures and the isolation structures within the trenches. The semiconductive pillars are in electrical contact with the conductive contact structures. Additional conductive contact structures are formed on upper surfaces of the semiconductive pillars. A device, a memory device, and an electronic system are also described.

公开(公告)号：US11527620B2

公开(公告)日：2022-12-13

申请号：US17317668

申请日：2021-05-11

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Deepak Chandra Pandey ,  Haitao Liu ,  Richard J. Hill ,  Guangyu Huang ,  Yunfei Gao ,  Ramanathan Gandhi ,  Scott E. Sills

IPC: H01L29/267 ,  H01L29/786 ,  H01L27/108 ,  H01L29/207 ,  H01L29/08 ,  H01L29/16

Abstract: Some embodiments include an integrated assembly having a polycrystalline first semiconductor material, and having a second semiconductor material directly adjacent to the polycrystalline first semiconductor material. The second semiconductor material is of a different composition than the polycrystalline first semiconductor material. A conductivity-enhancing dopant is within the second semiconductor material. The conductivity-enhancing dopant is a neutral-type dopant relative to the polycrystalline first semiconductor material. An electrical gate is adjacent to a region of the polycrystalline first semiconductor material and is configured to induce an electric field within said region of the polycrystalline first semiconductor material. The gate is not adjacent to the second semiconductor material.

公开(公告)号：US20220271127A1

公开(公告)日：2022-08-25

申请号：US17182737

申请日：2021-02-23

Applicant: Micron Technology, Inc.

Inventor： Ramanathan Gandhi ,  Augusto Benvenuti ,  Giovanni Maria Paolucci

IPC: H01L29/10 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/788 ,  H01L29/792

Abstract: A transistor comprises a channel region having a frontside and a backside. The channel region comprises a frontside channel material at the frontside and a backside channel material at the backside. A gate is adjacent the frontside of the channel region, with a gate insulator being between the gate and the channel region. The frontside channel material has total n-type dopant therein of greater than 1×1018 atoms/cm3 to no greater than 1×1020 atoms/cm3. The backside channel material has total n-type dopant therein of 0 atoms/cm3 to 1×1018 atoms/cm3. Other embodiments and aspects are disclosed.

公开(公告)号：US20220238658A1

公开(公告)日：2022-07-28

申请号：US17720032

申请日：2022-04-13

Applicant: Micron Technology, Inc.

Inventor： Yi Fang Lee ,  Isamu Asano ,  Ramanathan Gandhi ,  Scott E. Sills

IPC: H01L29/22 ,  H01L29/786 ,  G11C11/402 ,  H01L27/108

Abstract: Some embodiments include an integrated assembly having a gate material, an insulative material adjacent the gate material, and a semiconductor oxide adjacent the insulative material. The semiconductor oxide has a channel region proximate the gate material and spaced from the gate material by the insulative material. An electric field along the gate material induces carrier flow within the channel region, with the carrier flow being along a first direction. The semiconductor oxide includes a grain boundary having a portion which extends along a second direction that crosses the first direction of the carrier flow. In some embodiments, the semiconductor oxide has a grain boundary which extends along the first direction and which is offset from the insulative material by an intervening portion of the semiconductor oxide. The carrier flow is within the intervening region and substantially parallel to the grain boundary. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20210408294A1

公开(公告)日：2021-12-30

申请号：US17472895

申请日：2021-09-13

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills ,  Kirk D. Prall ,  Durai Vishak Nirmal Ramaswamy ,  Ramanathan Gandhi

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/06 ,  H01L27/11597 ,  H01L29/10 ,  H01L27/11514 ,  H01L29/08

Abstract: A device comprises an array comprising rows and columns of elevationally-extending transistors. An access line interconnects multiple of the elevationally-extending transistors along individual of the rows. The transistors individually comprise an upper source/drain region, a lower source/drain region, and a channel region extending elevationally there-between. The channel region comprises an oxide semiconductor. A transistor gate is operatively laterally-proximate the channel region and comprises a portion of an individual of the access lines. Intra-row-insulating material is longitudinally between immediately-intra-row-adjacent of the elevationally-extending transistors. Inter-row-insulating material is laterally between immediately-adjacent of the rows of the elevationally-extending transistors. At least one of the intra-row-insulating material and the inter-row-insulating material comprises void space. Other embodiments, including method embodiments, are disclosed.

公开(公告)号：US20210265467A1

公开(公告)日：2021-08-26

申请号：US17317668

申请日：2021-05-11

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Deepak Chandra Pandey ,  Haitao Liu ,  Richard J. Hill ,  Guangyu Huang ,  Yunfei Gao ,  Ramanathan Gandhi ,  Scott E. Sills

IPC: H01L29/267 ,  H01L29/786 ,  H01L27/108 ,  H01L29/207 ,  H01L29/08 ,  H01L29/16

Abstract: Some embodiments include an integrated assembly having a polycrystalline first semiconductor material, and having a second semiconductor material directly adjacent to the polycrystalline first semiconductor material. The second semiconductor material is of a different composition than the polycrystalline first semiconductor material. A conductivity-enhancing dopant is within the second semiconductor material. The conductivity-enhancing dopant is a neutral-type dopant relative to the polycrystalline first semiconductor material. An electrical gate is adjacent to a region of the polycrystalline first semiconductor material and is configured to induce an electric field within said region of the polycrystalline first semiconductor material. The gate is not adjacent to the second semiconductor material.

公开(公告)号：US20200295005A1

公开(公告)日：2020-09-17

申请号：US16298947

申请日：2019-03-11

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Yi Fang Lee ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy ,  Ramanathan Gandhi ,  Karthik Sarpatwari ,  Scott E. Sills ,  Sameer Chhajed

IPC: H01L27/105 ,  H01L27/092 ,  H01L27/12 ,  H01L29/24 ,  H01L29/267 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

Abstract: Some embodiments include an integrated assembly having a first semiconductor material between two regions of a second semiconductor material. The second semiconductor material is a different composition than the first semiconductor material. Hydrogen is diffused within the first and second semiconductor materials. The conductivity of the second semiconductor material increases in response to the hydrogen diffused therein to thereby create a structure having the second semiconductor material as source/drain regions, and having the first semiconductor material as a channel region between the source/drain regions. A transistor gate is adjacent the channel region and is configured to induce an electric field within the channel region. Some embodiments include methods of forming integrated assemblies.