公开(公告)号：US11579809B2

公开(公告)日：2023-02-14

申请号：US17332605

申请日：2021-05-27

Applicant: Micron Technology, Inc.

Inventor： Tingjun Xie ,  Zhengang Chen

IPC: G06F3/06 ,  G11C7/10 ,  G11C7/22

Abstract: A method described herein involves identifying a first time associated with a read operation that retrieves data of a write unit at a memory sub-system, identifying a second time associated with a write operation that stored the data of the write unit at the memory sub-system, and performing a refresh operation for the data of the write unit at the memory sub-system based on a difference between the first time associated with the read operation and the second time associated with the write operation.

公开(公告)号：US20220413714A1

公开(公告)日：2022-12-29

申请号：US17357436

申请日：2021-06-24

Applicant: Micron Technology, Inc.

Inventor： Guang Hu ,  Jianmin Huang ,  Zhengang Chen

IPC: G06F3/06

Abstract: A method includes determining one or more quality attributes for memory cells of a memory device, receiving a memory access request involving data written to at least a portion of the memory cells, and determining whether the memory access request corresponds to a random read operation or a sequential read operation. The method further includes responsive to determining that the memory access request corresponds to a random read operation or responsive to determining that the one or more quality attributes for memory cells are greater than a threshold quality level, or both, selecting a read mode for use in performance of the random read operation and performing the random read operation using the selected read mode.

公开(公告)号：US11526395B2

公开(公告)日：2022-12-13

申请号：US17100571

申请日：2020-11-20

Applicant: Micron Technology, Inc.

Inventor： Wei Wang ,  Jiangli Zhu ,  Ying Yu Tai ,  Ning Chen ,  Zhengang Chen ,  Cheng Yuan Wu

IPC: G06F11/07 ,  G11C29/52 ,  G06F11/10

Abstract: A read operation to retrieve data stored at a memory device is performed. Whether the data retrieved from the memory device includes an error that is not correctable is determined. Responsive to determining that the data retrieved from the memory device comprises the error that is not correctable, a buffer in a data path along which a write operation was performed to write the data at the memory device is searched for the data.

公开(公告)号：US11410743B2

公开(公告)日：2022-08-09

申请号：US17247254

申请日：2020-12-04

Applicant: Micron Technology, Inc.

Inventor： Tingjun Xie ,  Zhengang Chen

IPC: G11C29/50 ,  G06F11/30

Abstract: A processing device in a memory system determines a first error rate associated with a first number of bits written to the memory device as a first logical value and erroneously read as a second logical value and corresponding to a first range of a plurality of write-to-read delay times and a second error rate associated with a second number of bits written to the memory device as the second logical value and erroneously read as the first logical value and corresponding to the first range of the plurality of write-to-read delay times. The processing device further determines whether a ratio of the first error rate to the second error rate satisfies a first threshold criterion, and responsive to the ratio of the first error rate to the second error rate not satisfying the first threshold criterion, adjusts a read voltage level associated with the first range.

公开(公告)号：US11341046B2

公开(公告)日：2022-05-24

申请号：US16531305

申请日：2019-08-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Mikai Chen ,  Zhengang Chen ,  Charles See Yeung Kwong

IPC: G06F12/06 ,  G06F12/02

Abstract: Data can be received to be stored at a memory component. A first location of a first layer of the memory component to store a first portion of the data can be determined. A second location of a second layer of the memory component to store a second portion of the data can be determined, where the second layer is different from the first layer. The first portion of the data can be stored at the first layer of the memory component and the second portion of the data can be stored at the second layer of the memory component.

公开(公告)号：US11256429B2

公开(公告)日：2022-02-22

申请号：US16933577

申请日：2020-07-20

Applicant: Micron Technology, Inc.

Inventor： Zhenlei E. Shen ,  Zhengang Chen ,  Tingjun Xie ,  Jiangli Zhu

IPC: G06F3/06 ,  G11C13/00

Abstract: First data can be received at a memory sub-system. An operating temperature of the memory sub-system can be identified. An adjusted read voltage level can be determined in response to the operating temperature satisfying a threshold criterion pertaining to a threshold temperature. A read operation can be performed at the memory sub-system based on the adjusted read voltage level to retrieve second data. The first data can be stored at the memory sub-system based on the second data that was retrieved from the read operation that is based on the adjusted read voltage level.

公开(公告)号：US11146291B2

公开(公告)日：2021-10-12

申请号：US16806777

申请日：2020-03-02

Applicant: Micron Technology, Inc.

Inventor： Eyal En Gad ,  Zhengang Chen ,  Sivagnanam Parthasarathy ,  Yoav Weinberg

IPC: G06F11/00 ,  G06F11/30 ,  G08C25/00 ,  H03M13/00 ,  H04L1/00 ,  H03M13/11 ,  H03M13/09 ,  H03M13/29 ,  H03M13/15

Abstract: A processing device in a memory system reads a sense word from a memory device and executes a plurality of parity check equations on corresponding subsets of the sense word to determine a plurality of parity check equation results. The processing device determines a syndrome for the sense word using the plurality of parity check equation results, determines whether the syndrome for the sense word satisfies a codeword criterion, and responsive to the syndrome for the sense word not satisfying the codeword criterion, performs an iterative LDPC correction process, wherein at least one iteration after a first iteration in the LDPC correction process uses a criterion based at least partially on a previous iteration or partial iteration.

公开(公告)号：US11056166B2

公开(公告)日：2021-07-06

申请号：US16514840

申请日：2019-07-17

Applicant: Micron Technology, Inc.

Inventor： Tingjun Xie ,  Seungjune Jeon ,  Zhengang Chen ,  Zhenlei Shen ,  Charles See Yeung Kwong

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/16

Abstract: A refresh operation can be performed at a memory sub-system The refresh operation can performed at a current frequency. A write count associated with the memory sub-system can be received. A determination can be made as to whether the write count associated with the memory sub-system satisfies a write count threshold. In response to determining that the write count associated with the memory sub-system satisfies the write count threshold, the refresh operation can be performed at an increased frequency relative to the current frequency.

公开(公告)号：US11023172B2

公开(公告)日：2021-06-01

申请号：US16523851

申请日：2019-07-26

Applicant: Micron Technology, Inc.

Inventor： Zhengang Chen ,  Tingjun Xie

IPC: G06F12/00 ,  G06F3/06 ,  G11C16/10 ,  G06F16/245 ,  G11C16/26

Abstract: A system includes a memory component; and a processing device, operatively coupled with the memory component. The processing device is to receive a request to perform a read operation on data stored at a physical address of the memory component and determine whether the data satisfies a threshold criterion pertaining to when the data was written to the physical address. In response to the data satisfying the threshold criterion, the processing device is to perform the read operation on the data stored at the physical address using a first read voltage level, and in response to the data not satisfying the threshold criterion, perform the read operation on the data stored at the physical address using a second read voltage level.

公开(公告)号：US11004534B2

公开(公告)日：2021-05-11

申请号：US16533498

申请日：2019-08-06

Applicant: Micron Technology, Inc.

Inventor： Tingjun Xie ,  Zhengang Chen

IPC: G11C29/50 ,  G06F3/06

Abstract: A processing device in a memory sub-system receives a read request from a host system, the read request identifying data stored in a segment of a memory component, and performs a first read operation on the segment using a first read voltage level. The processing device determines whether the data read during the first read operation was successfully decoded. If so, the processing device determines a write-to-read (W2R) delay time for the segment and determines whether the W2R delay time within a first W2R delay range, wherein the first W2R delay range represents a first plurality of W2R delay times corresponding to the first read voltage level. Responsive to the W2R delay time for the segment not falling within the first W2R delay range, the processing device performs a read refresh operation on at least a portion of the segment using an applicable read voltage level.