公开(公告)号：US4954866A

公开(公告)日：1990-09-04

申请号：US247250

申请日：1988-09-21

申请人： Hirotoshi Tanaka ,  Hiroki Yamashita ,  Noboru Masuda ,  Junji Shigeta ,  Yasunari Umemoto ,  Osamu Kagaya

发明人： Hirotoshi Tanaka ,  Hiroki Yamashita ,  Noboru Masuda ,  Junji Shigeta ,  Yasunari Umemoto ,  Osamu Kagaya

IPC分类号： H01L27/06 ,  H01L27/105 ,  H01L27/11

CPC分类号： H01L27/1104 ,  H01L27/0605 ,  H01L27/1116 ,  H01L27/105

摘要： A semiconductor integrated circuit memory is disclosed in which a first impurity-doped layer for making circuit elements such as MESFET's and a second impurity-doped layer opposite in conductivity type to the first impurity-doped layer are formed in a semi-insulating substrate in such a manner that the second impurity-doped layer is formed under and between circuit elements for making up a memory cell array part and a peripheral circuit part, and is divided into at least first and second regions. For example, the first region formed under and between the circuit elements of the memory cell array part is made of a P-type layer which is high in carrier density, and the second region formed under and between the circuit elements of the peripheral circuit part is made of a P-type layer which is low in carrier density. The high carrier-density P-type layer formed under the memory cell array part allows a memory cell having a minimum critical charge for alpha-particles to gain satisfactory alpha-particle immunity even when the memory cell is made fine in size. Further, the low carrier-density P-type layer formed under the peripheral circuit part having a critical charge larger than that of the memory cell can improve the alpha-particle immunity of the peripheral circuit part and can suppress an increase in parasitic capacitance at the peripheral circuit part to maintain the high-speed operation of the memory.

摘要翻译： 公开了一种半导体集成电路存储器，其中在半绝缘衬底中形成用于制造电路元件的第一杂质掺杂层，例如MESFET和与第一杂质掺杂层的导电类型相反的第二杂质掺杂层 第二杂质掺杂层形成在用于构成存储单元阵列部分的电路元件和外围电路部分之间的方式，并且被划分为至少第一和第二区域。 例如，形成在存储单元阵列部分的电路元件之下和之间的第一区域由载流子密度高的P型层制成，并且第二区域形成在外围电路部分的电路元件之下 由载流子浓度低的P型层构成。 形成在存储单元阵列部分下方的高载流子密度P型层允许具有最小临界电荷的存储单元获得满意的α粒子免疫，即使当存储单元的尺寸精细时。 此外，形成在具有大于存储单元的临界电荷的外围电路部分下的低载流子密度P型层可以改善外围电路部分的α粒子免疫力，并且可以抑制在外部电路部分的寄生电容的增加 外围电路部分保持高速运行的内存。

公开(公告)号：US4723082A

公开(公告)日：1988-02-02

申请号：US884896

申请日：1986-07-14

申请人： Michio Asano ,  Akira Masaki ,  Masaru Osani ,  Minoru Yamada ,  Kenichi Ishibashi ,  Noboru Masuda

发明人： Michio Asano ,  Akira Masaki ,  Masaru Osani ,  Minoru Yamada ,  Kenichi Ishibashi ,  Noboru Masuda

IPC分类号： H01L27/00 ,  H01L21/3205 ,  H01L21/822 ,  H01L23/52 ,  H01L27/04 ,  H03K19/0185 ,  H03K19/017 ,  H03K19/094

CPC分类号： H03K19/018521 ,  H03K19/018557

摘要： A laminated multilayer electric circuit is comprised of wafers having each internal electric circuits and laminated one after another. A signal transfer circuit used in the laminated multilayer electric circuit for transfer of signals between the wafers through an electrostatic capacitor has a receiving circuit of sufficiently high input resistance for receiving a signal from a capacitance electrode forming the electrostatic capacitor, and a circuit for clamping the level of the signal substantially within the input amplitude for the receiving circuit. The signal transfer circuit permits the signal transfer to be performed not through a flip-flop or the like and consequently at high speeds.

摘要翻译： 叠层多层电路由具有每个内部电路并且彼此层叠的晶片组成。 在用于通过静电电容器在晶片之间传递信号的叠层多层电路中使用的信号传输电路具有足够高的输入电阻的接收电路，用于从形成静电电容器的电容电极接收信号，以及用于钳位 信号的电平基本上在接收电路的输入幅度内。 信号传送电路允许不通过触发器等执行信号传送，并且因此以高速执行信号传送。

公开(公告)号：US4697110A

公开(公告)日：1987-09-29

申请号：US555618

申请日：1983-11-28

申请人： Noboru Masuda ,  Michio Asano ,  Takehisa Hayashi ,  Hirotoshi Tanaka ,  Akira Masaki

发明人： Noboru Masuda ,  Michio Asano ,  Takehisa Hayashi ,  Hirotoshi Tanaka ,  Akira Masaki

IPC分类号： H03K19/003 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/0952 ,  H03K17/14 ,  H03K19/094

CPC分类号： H03K19/0952 ,  H03K19/00384 ,  H03K19/01707 ,  H03K19/018535

摘要： An input buffer for a semiconductor circuit is provided with a source follower circuit composed of a first FET whose gate electrode has an input connected thereto, and a second FET of the same conductivity type as that of the first FET, whose drain electrode is connected to a source electrode of the first FET directly or through at least one level-shifting diode and whose gate electrode is supplied with a control voltage. The input buffer also includes a FET inverter circuit connected to the drain electrode of the second FET directly or through at least one level-shifting diode. An output signal for the input buffer is derived from the FET inverter circuit. A particular advantage of the present invention is that it permits the input buffer to switch its output from one level to another in response to input signals falling within a predetermined voltage range regardless of logic threshold level fluctuations in the FETs and fluctuations in supply voltages coupled to the input buffer.

摘要翻译： 用于半导体电路的输入缓冲器设置有源极跟随器电路，该源极跟随器电路由其栅极具有与其连接的输入端的第一FET和与第一FET的导电类型相同的第二FET组成，漏极连接到 直接或通过至少一个电平移位二极管的第一FET的源极，并且其栅电极被提供控制电压。 输入缓冲器还包括直接或通过至少一个电平移位二极管连接到第二FET的漏电极的FET反相器电路。 输入缓冲器的输出信号是从FET反相器电路得出的。 本发明的一个特别优点在于，它允许输入缓冲器响应于处于预定电压范围内的输入信号而将其输出从一个电平切换到另一个电平，而与FET中的逻辑阈值电平波动无关，并且耦合到 输入缓冲区。

公开(公告)号：US4145687A

公开(公告)日：1979-03-20

申请号：US618155

申请日：1975-09-30

申请人： Noboru Masuda

发明人： Noboru Masuda

IPC分类号： H03M11/20 ,  G06F3/02

CPC分类号： H03M11/20

摘要： A keyboard switch circuit comprises a first plurality of terminals associated with m rows and a second plurality of terminals associated n columns. A plurality of series circuits each including a reluctance element and a diode are connected between the terminals associated with the rows and the columns, respectively, in a manner to correspond with key switches. By applying input pulse signals to the terminals of the rows, a keyboard signal corresponding to a key depressed is derived in the form of pulses on the terminals associated with the columns.

摘要翻译： 键盘开关电路包括与m行相关联的第一多个终端和与n列相关联的第二多个终端。 各自包括磁阻元件和二极管的多个串联电路分别以与键开关对应的方式分别连接在与行和列相关联的端子之间。 通过向行的端子施加输入脉冲信号，在与列相关联的终端上以脉冲的形式导出对应于键的键盘信号。

公开(公告)号：US4117523A

公开(公告)日：1978-09-26

申请号：US767311

申请日：1977-02-10

申请人： Noboru Masuda ,  Yu Nishino ,  Hiroaki Kase

发明人： Noboru Masuda ,  Yu Nishino ,  Hiroaki Kase

IPC分类号： G06K7/08 ,  G11B5/33 ,  G11B5/37 ,  G11B23/00 ,  G11B5/22 ,  G11B5/10 ,  G11B5/20

CPC分类号： G11B5/33 ,  G06K7/087 ,  G11B23/0007 ,  G11B5/37

摘要： A magnetic sensor includes a housing in which flux producing means which comprises an electromagnet or a permanent magnet is received. A pair of magnetoelectric transducer elements are secured to a surface of the flux producing means which represents a magnetic pole, with a given spacing between the elements. In order to dispose the magnetoelectric transducer elements as close as possible to the outer surface of the housing, the latter is formed with a through opening at a corresponding position. The through opening is covered by a thin shield cap to protect the magnetoelectric transducer elements from a member being detected which is passed in sliding contact with or very close to the outer surface of the housing and to provide an enclosed construction for the housing.

公开(公告)号：US3937764A

公开(公告)日：1976-02-10

申请号：US314033

申请日：1972-12-11

申请人： Hideichi Horikawa ,  Shitomi Katayama ,  Hajime Serita ,  Noboru Masuda

发明人： Hideichi Horikawa ,  Shitomi Katayama ,  Hajime Serita ,  Noboru Masuda

IPC分类号： C08F8/00 ,  C08L39/04

CPC分类号： C08F8/00

摘要： Polymer electrolyte compositions having polymerized monomer units of the structural formula: ##SPC1##Or acidic or alkaline salts of these compositions. R.sub.1 and R.sub.2 are hydrogen, methyl or ethyl. Also disclosed are methods for producing these compositions by reacting .beta.-propiolactone and a polymer composition including vinylpyridine monomer units, by hydrolyzing a neutral salt of the above structural formula to obtain a N-(2-carboxyethyl) poly- .gamma. -vinylpyridine acidic or alkaline salt, by reacting the N-(2-carboxyethyl) poly- .gamma. -vinyl-pyridine salt with an acid or alkali to form a corresponding acid, neutral or alkaline salt, and by reacting a diluted or weak acid or alkali under nonhydrolyzing conditions with a polymer of the above structural formula to form a corresponding acidic, neutral or basic salt.

公开(公告)号：US08782900B2

公开(公告)日：2014-07-22

申请号：US13190665

申请日：2011-07-26

申请人： Yukihiro Hiramoto ,  Noboru Masuda

发明人： Yukihiro Hiramoto ,  Noboru Masuda

IPC分类号： B21D53/10

CPC分类号： B23P13/02 ,  B23P15/00 ,  Y10T29/49025 ,  Y10T29/49636 ,  Y10T29/49639 ,  Y10T29/49696 ,  Y10T29/49885 ,  Y10T29/49996

摘要： A manufacturing method of a rotating device includes a first machining process of machining a bearing hole while supplying a first cutting lubricant to a base member, a second machining process continuous from the first machining process, the second machining process being of machining a tap hole while supplying a second cutting lubricant to the base member, a blowing process of blowing at least either one of the bearing hole and the tap hole with a fluid in order to eliminate a machining residue, the blowing process including an air spraying process and a liquid spraying process, a cleaning process of cleaning the base member, and an assembling process of assembling the base member with the bearing unit and the rotating body.

摘要翻译： 旋转装置的制造方法包括在向基材供给第一切削润滑剂的同时加工轴承孔的第一加工工序，从第一加工工序连续的第二加工工序，第二加工工序是加工出孔， 向所述基座部件供给第二切削润滑剂，利用流体吹送所述轴承孔和所述排出孔中的至少一个的吹塑工序，以消除机械残留物，所述吹塑法包括空气喷涂法和喷液法 过程，清洁基座构件的清洁过程以及组装基座与轴承单元和旋转体的组装过程。

公开(公告)号：US07041336B2

公开(公告)日：2006-05-09

申请号：US10617865

申请日：2003-07-14

申请人： Noboru Masuda ,  Masaru Watanabe

发明人： Noboru Masuda ,  Masaru Watanabe

IPC分类号： B05D1/26

CPC分类号： B05C11/1047 ,  B05C5/0258 ,  B05C11/10 ,  B05D1/26 ,  B05D5/00 ,  B05D2252/02

摘要： The intermittent coating apparatus which includes a nozzle 1 which applies a paint 6 to a base material, a feeding side two-way valve 10 which repeats feeding of the paint 6 to the nozzle 1 and stop of the feeding, a return side two-way valve which 11 repeats discharge of the paint 6 to a return side and stop of the discharge, a paint flow path 12, means to feed the paint 6 into the flow path 12, and paint returning means 5 which repeats suction and return of the paint 6 out of and into the nozzle 1, and is characterized in that switching of the feeding side two-way valve 10 is carried out earlier than that of the return side two-way valve 11 within a range not shorter than 5 msec and not longer than 100 msec at least at a coating start time.

摘要翻译： 间歇式涂布装置，其具有将涂料6涂布在基材上的喷嘴1，重复向喷嘴1供给涂料6并停止供给的供给侧二通阀10，返回侧双向 阀11重复将油漆6排出到返回侧并停止排出，油漆流动路径12，将油漆6进料到流路12中的装置以及重复抽吸和返回涂料的涂料返回装置5 6，其特征在于，在不短于5毫秒的范围内，进给侧开闭阀10的切换比返回侧开闭阀11的切换早 至少在涂层开始时间超过100毫秒。

公开(公告)号：US06963754B2

公开(公告)日：2005-11-08

申请号：US10078381

申请日：2002-02-21

申请人： Noboru Masuda ,  Kiyoshi Kawamoto ,  Satoshi Masuda

发明人： Noboru Masuda ,  Kiyoshi Kawamoto ,  Satoshi Masuda

IPC分类号： H04B7/26 ,  H04B7/005 ,  H04W36/18 ,  H04W52/08 ,  H04W52/40 ,  H04B7/00

CPC分类号： H04W52/40 ,  H04W36/18 ,  H04W52/08

摘要： Disclosed is a transmission power control method which enables communications between a base station and a terminal station to be always performed at a high transfer rate by always assuring an uplink communication path between a base station which can transfer a downlink signal most efficiently and a terminal station. Each of terminal stations 111 to 119 selects a base station which can receive a downlink radio wave with the highest power, and transmits a code for identifying the base station on an uplink signal. When the received power of the uplink radio waves transmitted from the terminal station which has transmitted the code identifying the own station is higher than the threshold value, each of base stations 501 to 503 transmits a control signal for decreasing the power to the terminal station. When the terminal station sends a code for identifying another station or the power of the uplink radio waves received from the terminal station is lower than the threshold value, a control signal for increasing the power is sent to the terminal station. When even one power control signal for giving instruction to decrease the transmission power exists, each terminal station decreases its transmission power. When there is not the power control signal, each terminal station increases its transmission power.

摘要翻译： 公开了一种发送功率控制方法，其通过始终确保可以最有效地传送下行链路信号的基站与终端站之间的上行链路通信路径，使基站和终端站之间的通信始终以高传输速率进行通信 。 终端站111至119中的每一个选择能够接收具有最高功率的下行链路无线电波的基站，并且在上行链路信号上发送用于识别基站的码。 当从发送了本台站的代码的终端发送的上行无线电波的接收功率高于阈值时，基站501〜503中的每一个向终端站发送降低功率的控制信号。 当终端发送用于识别另一站的码或从终端接收到的上行电波的功率低于阈值时，向终端发送增加电力的控制信号。 当存在用于给出降低发送功率的指令的一个功率控制信号时，每个终端站降低其发送功率。 当没有功率控制信号时，每个终端站增加其发射功率。

公开(公告)号：US06768387B1

公开(公告)日：2004-07-27

申请号：US09634544

申请日：2000-08-08

申请人： Noboru Masuda ,  Hiroki Yamashita

发明人： Noboru Masuda ,  Hiroki Yamashita

IPC分类号： H03B100

CPC分类号： H03L7/087 ,  H03K3/011 ,  H03K3/0315 ,  H03L7/0895 ,  H03L7/093 ,  H03L7/0995

摘要： The present invention relates to a PLL circuit and a voltage controlled oscillator wherein a clock signal jitter caused when the supply voltage fluctuates of which is small can be supplied, and the voltage controlled oscillator is provided with a MOS transistor to one end of which a first power source (Vss) is connected and to the gate electrode of which a control signal for controlling the oscillation frequency is input, an oscillator connected between the other end of the MOS transistor and a second power source (Vdd) and a capacitative element connected to the oscillator in parallel and is further provided with additive control means for minutely controlling the oscillation frequency.

摘要翻译： 本发明涉及一种PLL电路和压控振荡器，其中可以提供当电源电压波动小时引起的时钟信号抖动，并且压控振荡器设置有MOS晶体管，其一端为第一 电源（Vss）连接到输入用于控制振荡频率的控制信号的栅电极，连接在MOS晶体管的另一端和第二电源（Vdd）之间的振荡器和连接到 该振荡器并联并且还具有用于微调控制振荡频率的附加控制装置。