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33 条记录 (耗时 0.029 秒)

    Output circuit having transistor monitor for matching output impedance to load impedance
    3.
    发明授权
    Output circuit having transistor monitor for matching output impedance to load impedance 失效
    输出电路具有晶体管监视器，用于将输出阻抗与负载阻抗匹配

    公开(公告)号：US4719369A

    公开(公告)日：1988-01-12

    申请号：US894103

    申请日：1986-08-07

    申请人： Michio Asano ,  Akira Masaki ,  Kenichi Ishibashi

    发明人： Michio Asano ,  Akira Masaki ,  Kenichi Ishibashi

    IPC分类号： G05F3/24 ,  H03H11/24 ,  H03K19/00 ,  H03K19/003 ,  H03K17/16 ,  H03K17/687

    CPC分类号： H03H11/245 ,  G05F3/24 ,  H03K19/0005 ,  H03K19/00361 ,  H01L2924/0002

    摘要： An output circuit comprises an output transistor circuit for applying an output signal to a transmission line connected to an output terminal, a circuit for driving the output transistor circuit in response to an input signal applied to an input terminal, and a control circuit by which the signal amplitude of a first wave applicable to the transmission line with a load connected to the output terminal through the transmission line is rendered approximately one half of the output signal amplitude with a load directly connected to the output terminal. The control circuit includes a monitoring transistor within the same chip as the output transistor circuit, a selected one of the output resistance and input signal of the output transistor circuit being controlled in accordance with the magnitude of the drain current of the monitoring transistor to adjust the amplitude of the signal applied to the transmission line. Transmission with transmitting and receiving ends having a well-defined transmission waveform is obtained, thereby making possible high-speed signal transmission between LSI chips.

    摘要翻译： 输出电路包括：输出晶体管电路，用于将输出信号施加到连接到输出端子的传输线;响应于施加到输入端子的输入信号驱动输出晶体管电路的电路;以及控制电路， 通过传输线连接到输出端的负载的第一波的第一波的信号幅度大约是输出信号幅度的一半，负载直接连接到输出端。 控制电路包括在与输出晶体管电路相同的芯片内的监控晶体管，根据监控晶体管的漏极电流的大小来控制输出晶体管电路的输出电阻和输入信号中选定的一个，以调整 施加到传输线的信号的振幅。 获得具有良好定义的传输波形的发送和接收端的传输，从而在LSI芯片之间实现高速信号传输。

    High speed clock distribution system
    4.
    发明授权
    High speed clock distribution system 失效
    高速时钟分配系统

    公开(公告)号：US5087829A

    公开(公告)日：1992-02-11

    申请号：US443503

    申请日：1989-12-01

    申请人： Kenichi Ishibashi ,  Takehisa Hayashi ,  Toshio Doi ,  Mitsuo Asai ,  Noboru Masuda ,  Akira Yamagiwa ,  Toshihiro Okabe

    发明人： Kenichi Ishibashi ,  Takehisa Hayashi ,  Toshio Doi ,  Mitsuo Asai ,  Noboru Masuda ,  Akira Yamagiwa ,  Toshihiro Okabe

    IPC分类号： H03K5/15

    CPC分类号： H03K5/15

    摘要： This invention discloses a clock distribution system which distributes a first clock signal as a reference clock as the reference for the phase and frequency to each processing unit (e.g. LSI) and generates a multi-phase second clock signal to be used in each processing unit by a delay circuit group whose delay time is adjusted. The clock distribution system comprises a clock generation block for generating a one-phase reference clock; a first control loop for comparing the phase of the reference clock with the phase of a feedback signal and adjusting the phase of the reference clock so that their phases are in agreement; and a second control loop including a delay circuit group consisting of a plurality of variable delay circuits to which the reference clock phase-adjusted by the first control loop is inputted and which are connected in series, and means for generating a multi-phase clock signal by use of the output signal of each of the plurality of variable delay circuits and the phase-adjusted referencde clock, controlling the delay time of the plurality of variable delay circuits so as to accomplish a predetermined relation with the period of the phase-adjusted reference clock and applying one of the multi-phase clock signals as the feedback signal described above to the first control loop.

    摘要翻译： 本发明公开了一种时钟分配系统，其将作为基准时钟的第一时钟信号作为相位和频率的参考分配给每个处理单元（例如，LSI），并且通过以下方式生成要在每个处理单元中使用的多相第二时钟信号： 延迟时间被调整的延迟电路组。 时钟分配系统包括用于产生单相参考时钟的时钟产生模块; 第一控制环路，用于将参考时钟的相位与反馈信号的相位进行比较，并且调整参考时钟的相位，使得它们的相位一致; 以及包括由多个可变延迟电路组成的延迟电路组的第二控制回路，所述多个可变延迟电路输入由第一控制回路相位调整的参考时钟并串联连接的参考时钟，以及用于产生多相时钟信号的装置 通过使用多个可变延迟电路中的每一个的输出信号和相位调整参考时钟，控制多个可变延迟电路的延迟时间，以便与相位调整参考的周期完成预定的关系 时钟，并将多相时钟信号中的一个作为上述反馈信号施加到第一控制回路。

    ELECTRIC WIRE OR CABLE
    6.
    发明申请
    ELECTRIC WIRE OR CABLE 有权
    电线或电缆

    公开(公告)号：US20120118607A1

    公开(公告)日：2012-05-17

    申请号：US13382506

    申请日：2010-07-06

    申请人： Kenichi Ishibashi ,  Kazumi Mochizuki ,  Yasunobu Kondo

    发明人： Kenichi Ishibashi ,  Kazumi Mochizuki ,  Yasunobu Kondo

    IPC分类号： H01B5/00 ,  B21C1/00

    CPC分类号： H01B1/023 ,  C22C21/00 ,  C22C21/02 ,  C22C21/06 ,  C22C21/08 ,  C22C21/12 ,  C22C21/14 ,  C22C21/16 ,  C22F1/04

    摘要： There is provided an aluminum-alloy material having sufficient electric conductivity and tensile strength as a wiring material and excellent in wire-drawing property, and an electric wire or cable using the same. An electric wire or cable includes an aluminum-alloy strand formed of an aluminum-alloy including Fe: 0.1% by mass or more to less than 1.0% by mass, Zr: 0 to 0.08% by mass, Si: 0.02 to 2.8% by mass, at least one of Cu: 0.05 to 0.63% by mass and Mg: 0.04 to 0.45% by mass, and the remainder being aluminum and unavoidable impurities.

    摘要翻译： 提供具有足够的导电性和拉伸强度的铝合金材料作为布线材料并且拉拔性优良，以及使用该铝合金材料的电线或电缆。 电线或电缆包括由铝合金形成的铝合金线，所述铝合金包含Fe：0.1质量％以上至小于1.0质量％，Zr：0〜0.08质量％，Si：0.02〜2.8质量％ 质量，Cu中的至少一种：0.05〜0.63质量％，Mg：0.04〜0.45质量％，余量为铝和不可避免的杂质。

    Semiconductor integrated circuit system having function of automatically adjusting output resistance value
    8.
    发明授权
    Semiconductor integrated circuit system having function of automatically adjusting output resistance value 失效
    具有自动调节输出电阻值功能的半导体集成电路系统

    公开(公告)号：US06049221A

    公开(公告)日：2000-04-11

    申请号：US111804

    申请日：1998-07-08

    申请人： Kenichi Ishibashi ,  Takehisa Hayashi ,  Tsutomu Goto ,  Hideki Murayama ,  Akira Yamagiwa ,  Yasuhiro Ishii ,  Naoki Hamanaka ,  Masabumi Shibata

    发明人： Kenichi Ishibashi ,  Takehisa Hayashi ,  Tsutomu Goto ,  Hideki Murayama ,  Akira Yamagiwa ,  Yasuhiro Ishii ,  Naoki Hamanaka ,  Masabumi Shibata

    IPC分类号： H03K19/003 ,  H03K19/00 ,  H03K19/0175 ,  H04L25/02 ,  H03K19/175

    CPC分类号： H03K19/0005

    摘要： A semiconductor integrated circuit system having a function of automatically adjusting an output resistance value with reference to a temperature of an LSI which is operating. When a count value obtained from a counter by counting the output of a timer becomes equal to a predetermined value, a temperature sensor measures temperatures of LSIs. If a temperature fluctuation measured from a previous measured value is greater than a predetermined width, then a control apparatus issues an output resistance value adjustment request signal to output resistance adjustment units of the LSIs. When receiving the output resistance value adjustment request signal, the output resistance value adjustment units stop the signal transmission between the LSIs, adjust output resistance values of output circuits in such a manner that the output resistance values are matched with a characteristic impedance of a transmission line, and maintains the adjusted output resistance values until the output resistance value adjustment units receive next output resistance value adjustment request signal.

    摘要翻译： 具有参照正在运行的LSI的温度来自动调整输出电阻值的功能的半导体集成电路系统。 当通过对计时器的输出进行计数而得到的计数值等于预定值时，温度传感器测量LSI的温度。 如果从先前测量值测量的温度波动大于预定宽度，则控制装置发出输出电阻值调整请求信号以输出LSI的电阻调节单元。 当接收到输出电阻值调整请求信号时，输出电阻值调节单元停止LSI之间的信号传输，以输出电阻值与传输线的特性阻抗匹配的方式调整输出电路的输出电阻值 并保持调整后的输出电阻值直到输出电阻值调整单元接收到下一个输出电阻值调整请求信号。

    Method and system for synchronizing data having skew
    9.
    发明授权
    Method and system for synchronizing data having skew 失效
    用于同步具有偏斜的数据的方法和系统

    公开(公告)号：US5867541A

    公开(公告)日：1999-02-02

    申请号：US441613

    申请日：1995-05-15

    申请人： Akira Tanaka ,  Kenichi Ishibashi ,  Takehisa Hayashi ,  Akira Yamagiwa

    发明人： Akira Tanaka ,  Kenichi Ishibashi ,  Takehisa Hayashi ,  Akira Yamagiwa

    IPC分类号： G06F13/42 ,  H04L7/00 ,  H04L7/033

    CPC分类号： H04L7/0337 ,  H04L7/0037 ,  H04L7/0008

    摘要： Data is transmitted from any one of a plurality of transmitters in synchronism with a first clock. A receiver receives the data in synchronism with the first clock and a second clock having a predetermined phase relationship with the first clock. Control information is previously held in the receiver regarding data reception conditions associated with the plurality of transmitters to control reception conditions of the receiver on the basis of the control information.

    摘要翻译： 数据从多个发射机中的任何一个与第一时钟同步发送。 接收机与第一时钟同步地接收数据，第二时钟与第一时钟具有预定的相位关系。 先前在接收机中保持与多个发射机有关的数据接收条件的控制信息，以根据控制信息来控制接收机的接收条件。