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41.发明申请REFERENCE SIGNAL GENERATING CIRCUIT, AD CONVERSION CIRCUIT, AND IMAGING DEVICE 有权参考信号发生电路，AD转换电路和成像装置公开(公告)号：US20140183336A1
公开(公告)日：2014-07-03
申请号：US14090569
申请日：2013-11-26
Applicant: OLYMPUS CORPORATION
Inventor： Yoshio Hagihara
CPC classification number: H03M1/34 , H03K2005/00241 , H03M1/56 , H04N5/3765 , H04N5/378
Abstract: A reference signal generating circuit, an AD conversion circuit, and an imaging device are provided. A clock generating unit includes a delay section including delay units, each of which delays an input signal and outputs a delayed signal, and outputs a low-order phase signal based on a signal output from the delay section. A high-order current source cell unit includes high-order current source cells, each of which generates the same constant current. A low-order current source cell unit includes low-order current source cells weighted to generate constant currents having current values that differ by a predetermined proportion of a current value of the constant current generated by the high-order current source cell. Selection of the high-order current source cell is performed based on a clock obtained by dividing a clock based on the low-order phase signal.
Abstract translation: 提供了参考信号发生电路，AD转换电路和成像装置。 时钟发生单元包括延迟部分，其包括延迟单元，每个延迟单元延迟输入信号并输出延迟信号，并且基于从延迟部分输出的信号输出低阶相位信号。 高阶电流源单元单元包括高阶电流源单元，每个单元产生相同的恒定电流。 低阶电流源单元单元包括加权的低阶电流源单元，以产生恒定电流，该恒定电流的电流值与由高阶电流源单元产生的恒定电流的当前值的预定比例相差。 基于通过基于低阶相位信号划分时钟而获得的时钟来执行高阶电流源单元的选择。
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公开(公告)号：US08704696B2
公开(公告)日：2014-04-22
申请号：US13683685
申请日：2012-11-21
Applicant: Olympus Corporation
Inventor： Yoshio Hagihara
CPC classification number: H03M1/56 , H01L27/146 , H03M1/123 , H03M1/14 , H03M1/34 , H03M1/502 , H03M1/60
Abstract: An AD conversion circuit includes a reference signal generation unit, which generates a reference signal, a comparison unit, which ends a comparison process at a timing at which the reference signal has satisfied a predetermined condition with respect to the analog signal, a first path in which a signal is transferred through each of n delay units, a clock signal generation unit, which outputs a lower-order phase signal, a latch unit, which latches the lower-order phase signal, a higher-order count unit including a first counter circuit, which acquires a higher-order count value by performing a count operation using a signal output from any one of the delay units, a calculation unit, which generates a lower-order count signal, and a lower-order count unit, which acquires a lower-order count value by performing the count operation using the lower-order count signal.
Abstract translation: AD转换电路包括：产生参考信号的参考信号生成单元，比较单元，其在参考信号相对于模拟信号满足预定条件的定时结束比较处理;第一路径， 信号通过n个延迟单元中的每一个传送，输出低阶相位信号的时钟信号生成单元，锁存低阶相位信号的锁存单元，包括第一计数器的高阶计数单元 电路，其通过使用从任一个延迟单元输出的信号，产生低阶计数信号的计算单元和下位计数单元执行计数操作来获取高阶计数值，所述计算单元获取 通过使用低阶计数信号执行计数操作来计算低位计数值。
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公开(公告)号：US08669898B2
公开(公告)日：2014-03-11
申请号：US13626533
申请日：2012-09-25
Applicant: Olympus Corporation
Inventor： Yoshio Hagihara
IPC: H03M1/56
CPC classification number: H04N5/3765 , H04N5/341 , H04N5/378
Abstract: Provided are a ramp wave generation circuit and a solid-state imaging device in which a pulse output unit includes a delay part including a plurality of delay units that delay and output an input signal, and a delay control part that controls a delay time by which the delay unit delays the signal, and outputs a plurality of signals having logic states corresponding to logic states of signals output by the delay units, a time difference between timings at which the logic states of the respective signals are changed being a time corresponding to the delay time.
Abstract translation: 提供了一种斜波生成电路和固态成像装置，其中脉冲输出单元包括延迟部分，延迟部分包括延迟和输出输入信号的多个延迟单元，以及延迟控制部分，其控制延迟时间， 延迟单元延迟信号，并且输出具有与由延迟单元输出的信号的逻辑状态相对应的逻辑状态的多个信号，各个信号的逻辑状态改变的定时之间的时间差为对应于 延迟时间。
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公开(公告)号：US20130134296A1
公开(公告)日：2013-05-30
申请号：US13683685
申请日：2012-11-21
Applicant: Olympus Corporation
Inventor： Yoshio Hagihara
IPC: H03M1/34 , H01L27/146
CPC classification number: H03M1/56 , H01L27/146 , H03M1/123 , H03M1/14 , H03M1/34 , H03M1/502 , H03M1/60
Abstract: An AD conversion circuit includes a reference signal generation unit, which generates a reference signal, a comparison unit, which ends a comparison process at a timing at which the reference signal has satisfied a predetermined condition with respect to the analog signal, a first path in which a signal is transferred through each of n delay units, a clock signal generation unit, which outputs a lower-order phase signal, a latch unit, which latches the lower-order phase signal, a higher-order count unit including a first counter circuit, which acquires a higher-order count value by performing a count operation using a signal output from any one of the delay units, a calculation unit, which generates a lower-order count signal, and a lower-order count unit, which acquires a lower-order count value by performing the count operation using the lower-order count signal.
Abstract translation: AD转换电路包括：产生参考信号的参考信号生成单元，比较单元，其在参考信号相对于模拟信号满足预定条件的定时结束比较处理;第一路径， 信号通过n个延迟单元中的每一个传送，输出低阶相位信号的时钟信号生成单元，锁存低阶相位信号的锁存单元，包括第一计数器的高阶计数单元 电路，其通过使用从任一个延迟单元输出的信号，产生低阶计数信号的计算单元和下位计数单元执行计数操作来获取高阶计数值，所述计算单元获取 通过使用低阶计数信号执行计数操作来计算低位计数值。
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公开(公告)号：US11843891B2
公开(公告)日：2023-12-12
申请号：US17189697
申请日：2021-03-02
Applicant: OLYMPUS CORPORATION
Inventor： Yoshio Hagihara
IPC: H04N25/772 , H01L27/146 , H04N25/75
CPC classification number: H04N25/772 , H01L27/14643 , H04N25/75
Abstract: An AD conversion device includes a comparison circuit, an upper-level DA conversion circuit, a level shift circuit, a lower-level DA conversion circuit, and a correction device. The comparison circuit includes a first terminal and a second terminal. The comparison circuit is configured to compare a first voltage level of a signal input to the first terminal with a second voltage level of a signal input to the second terminal. The upper-level DA conversion circuit includes a plurality of capacitance elements electrically connected to the second terminal. Capacitive values of the plurality of capacitance elements are weighted by binary numbers. The level shift circuit includes one or more capacitance elements electrically connected to the second terminal. The lower-level DA conversion circuit includes a plurality of capacitance elements electrically connected to the second terminal.
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Patent Agency Ranking
公开(公告)号：US11233967B2
公开(公告)日：2022-01-25
申请号：US16940748
申请日：2020-07-28
Applicant: OLYMPUS CORPORATION
Inventor： Yoshio Hagihara
IPC: H04N5/378 , G02B23/24 , H03M1/34 , H03M1/56 , H04N5/3745
Abstract: In an AD conversion circuit, a comparator is configured to compare a first voltage of a first input terminal with a second voltage of a second input terminal. A reset circuit is configured to reset a voltage of the first input terminal of the comparator and a voltage of the second input terminal of the comparator when a second analog signal is input to the first input terminal of the comparator. A first signal generation circuit is configured to generate the second analog signal having a third voltage higher or lower than a voltage of a first analog signal. The first analog signal is input to the first input terminal of the comparator after the voltage of the first input terminal of the comparator and the voltage of the second input terminal of the comparator are reset.
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公开(公告)号：US20210211600A1
公开(公告)日：2021-07-08
申请号：US17189697
申请日：2021-03-02
Applicant: OLYMPUS CORPORATION
Inventor： Yoshio Hagihara
IPC: H04N5/3745 , H04N5/378 , H01L27/146
Abstract: An AD conversion device includes a comparison circuit, an upper-level DA conversion circuit, a level shift circuit, a lower-level DA conversion circuit, and a correction device. The comparison circuit includes a first terminal and a second terminal. The comparison circuit is configured to compare a first voltage level of a signal input to the first terminal with a second voltage level of a signal input to the second terminal. The upper-level DA conversion circuit includes a plurality of capacitance elements electrically connected to the second terminal. Capacitive values of the plurality of capacitance elements are weighted by binary numbers. The level shift circuit includes one or more capacitance elements electrically connected to the second terminal. The lower-level DA conversion circuit includes a plurality of capacitance elements electrically connected to the second terminal.
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公开(公告)号：US10958283B2
公开(公告)日：2021-03-23
申请号：US16896494
申请日：2020-06-09
Applicant: OLYMPUS CORPORATION
Inventor： Yoshio Hagihara
Abstract: An AD conversion circuit includes a comparison circuit, a first DA conversion circuit including a plurality of resistance elements, and a first voltage output circuit. A comparator of the comparison circuit outputs a signal that represents a result of comparing a first voltage of a first input terminal with a second voltage of a second input terminal. A first combined resistance value of the first DA conversion circuit and the first voltage output circuit seen from a second terminal of the first capacitance element is a first value when the first capacitance element holds a first signal. The first combined resistance value is a second value when the comparator compares the first voltage with the second voltage. The first value is less than the second value.
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公开(公告)号：US10588487B2
公开(公告)日：2020-03-17
申请号：US15886262
申请日：2018-02-01
Applicant: OLYMPUS CORPORATION
Inventor： Yoshio Hagihara
Abstract: A signal transmission circuit includes an impedance conversion circuit and a current-voltage conversion circuit. A first current is input to the impedance conversion circuit. The impedance conversion circuit outputs a second current according to the first current. The current-voltage conversion circuit converts the second current output from the impedance conversion circuit into a voltage. The impedance conversion circuit includes a first current source and a current output circuit. The first current source generates a reference current. The current output circuit outputs the second current according to the difference between the first current and the reference current or the sum of the first current and the reference current.
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公开(公告)号：US10129496B2
公开(公告)日：2018-11-13
申请号：US15635516
申请日：2017-06-28
Applicant: OLYMPUS CORPORATION
Inventor： Yoshio Hagihara
Abstract: An imaging device includes an imaging unit, a reference signal generation unit, m (m is an integer of 3 or more) number of column delay units, and a plurality of column AD conversion units. The plurality of column delay units is arranged so as to correspond to two or more and less than m of the column AD conversion units. Each of the plurality of column delay units includes a first delay circuit. The first delay circuit generates a plurality of first delay clocks. The column AD conversion unit includes a comparison unit, a latch unit, and a counter unit. The comparison unit compares a pixel signal with a reference signal, and outputs a control signal corresponding to a comparison result. The latch unit includes a plurality of latch circuits that latches the plurality of first delay clocks on the basis of a state change of the control signal.
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