公开(公告)号：US4256928A

公开(公告)日：1981-03-17

申请号：US80169

申请日：1979-09-28

申请人： Ronald A. Lesea ,  Barrie Luttge ,  Austin H. Lesea

发明人： Ronald A. Lesea ,  Barrie Luttge ,  Austin H. Lesea

IPC分类号： H04M1/00 ,  H04M3/51 ,  H04M3/54

CPC分类号： H04M3/51 ,  H04M1/006

摘要： A telephone call diverting and answering system. The system includes a telephone call concentrator for diverting a telephone call placed at a telephone set at one of a number of calling stations, from a telephone line connected to the intended telephone set, at one of a large number of called stations, to one of a small number of telephone trunks leading to sets at a number of answering stations. The system further includes an operator console at each answering station, and a traffic director for assigning the call to a particular station by causing the identity of the called station and the number of the diverting trunk to be displayed on the operator console of the assigned answering station.

摘要翻译： 电话转接和应答系统。 该系统包括电话呼叫集中器，用于将在多个呼叫站之一处的电话机上的电话呼叫，从连接到预期电话机的电话线转移到大量呼叫站中的一个， 少数电话干线通往多个应答台。 该系统还包括在每个应答站的操作员控制台，以及一个交通总监，用于通过使被叫站的身份和转移中继线的号码被显示在所分配的答复的操作员控制台上来将呼叫分配给特定的站 站。

公开(公告)号：US08773929B1

公开(公告)日：2014-07-08

申请号：US12045864

申请日：2008-03-11

申请人： Austin H. Lesea

发明人： Austin H. Lesea

IPC分类号： G11C11/412 ,  G11C11/413 ,  G11C11/419 ,  H01L27/11

CPC分类号： H01L27/1104 ,  G11C11/4125

摘要： A memory cell (300) having a plurality of transistors connected so as to restore a data value to a node of the memory cell to an initial value following an event upsetting the initial value. A first transistor (306) of a first type is in a first well (334) of a second type having a first well tap (342). A second transistor (308) of the first type is in a second well (336) of the second type having a second well tap (344). A third transistor (310) of the second type is in a third well (338) of the first type having a third well tap (346); and a fourth transistor (312) of the second type is in a fourth well (340) of the first type having a fourth well tap (348). The first well, second well, third well, and forth well are isolated from each of the other wells.

摘要翻译： 连接有多个晶体管的存储单元（300），以便在使初始值变坏的事件之后将数据值恢复到存储单元的节点的初始值。 第一类型的第一晶体管（306）位于具有第一阱分接头（342）的第二类型的第一阱（334）中。 第二类型的第二晶体管（308）位于第二类型的第二阱（336）中，具有第二阱阱（344）。 第二类型的第三晶体管（310）位于具有第三阱分接头（346）的第一类型的第三阱（338）中; 并且第二类型的第四晶体管（312）位于具有第四阱分接头（348）的第一类型的第四阱（340）中。 第一口井，第二口井，第三口井和第三口井分别从每个其他井中分离出来。

公开(公告)号：US08595442B1

公开(公告)日：2013-11-26

申请号：US12947363

申请日：2010-11-16

申请人： Philip B. James-Roxby ,  Austin H. Lesea

发明人： Philip B. James-Roxby ,  Austin H. Lesea

IPC分类号： G06F12/16 ,  G06F11/00

CPC分类号： G06F11/1415 ,  G06F11/1004

摘要： Methods and systems redundantly validate values that are stored in a memory arrangement. The memory arrangement includes a first port and a second port that provide coherent access to one or more caches in the memory arrangement, and the first and second ports provide this coherent access at the same priority level. An instruction processor verifies that a first expected value matches a first check value calculated from the values as read from the memory arrangement via the first port. A check circuit verifies that a second expected value matches a second check value calculated from the values as read from the memory arrangement via the second port. A recovery operation is performed in response to the first or second expected values not matching the first and second check values, respectively.

摘要翻译： 方法和系统冗余验证存储在存储器排列中的值。 存储器装置包括提供对存储器装置中的一个或多个高速缓存的相干访问的第一端口和第二端口，并且第一和第二端口以相同的优先级提供这种一致的访问。 指令处理器验证第一期望值是否符合从通过第一端口从存储器装置读取的值计算出的第一检查值。 检查电路验证第二期望值是否符合从通过第二端口从存储器装置读取的值计算出的第二检查值。 响应于分别与第一和第二检查值不匹配的第一或第二预期值执行恢复操作。

公开(公告)号：US08522052B1

公开(公告)日：2013-08-27

申请号：US12755927

申请日：2010-04-07

申请人： Austin H. Lesea

发明人： Austin H. Lesea

IPC分类号： H04L9/00

CPC分类号： H04L9/003 ,  H03K19/1733

摘要： In one embodiment of the present invention a secure cryptographic device is provided. The device includes a power supply interface, a cryptographic processing block coupled to the power supply interface, a random number generator, and a complex multiplication circuit. The complex multiplication circuit has an output coupled to the power supply interface for modulating a power variation waveform detectable on the power supply interface. The complex multiplication circuit also has a first input coupled to an output of the random number generator and a second input coupled to the power supply interface.

摘要翻译： 在本发明的一个实施例中，提供了一种安全密码装置。 该装置包括电源接口，耦合到电源接口的加密处理块，随机数发生器和复数乘法电路。 复数乘法电路具有耦合到电源接口的输出，用于调制在电源接口上可检测的功率变化波形。 复数乘法电路还具有耦合到随机数发生器的输出的第一输入和耦合到电源接口的第二输入。

公开(公告)号：US08516339B1

公开(公告)日：2013-08-20

申请号：US13078172

申请日：2011-04-01

申请人： Austin H. Lesea ,  Stephen M. Trimberger

发明人： Austin H. Lesea ,  Stephen M. Trimberger

IPC分类号： G11C29/00

CPC分类号： G11C29/42 ,  G06F11/1012 ,  G11C11/41 ,  G11C29/44 ,  G11C29/52 ,  H03M13/2906 ,  H03M13/2927 ,  H03M13/37

摘要： A method of correcting adjacent bit errors in a memory is disclosed. The method comprises determining that there are errors in each set of two non-overlapping sets of the memory; changing a stored value of a memory cell of the memory until it is determined that a single error exists in the memory; identifying a location of the single error in the memory; and correcting the single error in the memory. A circuit for detecting adjacent bit errors in a memory having alternating even memory cells and odd memory cells is also disclosed.

摘要翻译： 公开了一种校正存储器中相邻位错误的方法。 该方法包括确定存储器的两组非重叠集合的每组中存在错误; 改变存储器的存储单元的存储值，直到确定存储器中存在单个错误为止; 识别存储器中单个错误的位置; 并纠正存储器中的单个错误。 还公开了一种用于检测具有交替的均匀存储单元和奇数存储单元的存储器中的相邻位错误的电路。

公开(公告)号：US08476601B1

公开(公告)日：2013-07-02

申请号：US12004968

申请日：2007-12-20

申请人： Joseph J. Fabula ,  Austin H. Lesea ,  Raymond J. Matteis

发明人： Joseph J. Fabula ,  Austin H. Lesea ,  Raymond J. Matteis

IPC分类号： G01N23/00

CPC分类号： G01N23/222 ,  G01N2223/6113

摘要： Systems and methods are provided for identifying an atomic element in proximity to an integrated circuit. Trace amounts of a contaminant are identifiable. The atomic element is exposed to neutron radiation to convert a portion of the atomic element into a radioactive isotope of the atomic element. Upsets are measured for the binary states of the memory cells of the integrated circuit during a time period following the exposure to the neutron radiation. The atomic element is identified from the upsets of the binary states of the memory cells of the integrated circuit.

摘要翻译： 提供了用于识别靠近集成电路的原子元件的系统和方法。 痕量的污染物是可识别的。 原子元素暴露于中子辐射以将原子元素的一部分转化为原子元素的放射性同位素。 在暴露于中子辐射之后的一段时间内，对集成电路的存储单元的二进制状态进行测量。 根据集成电路的存储单元的二进制状态的不匹配来识别原子元素。

公开(公告)号：US08397191B1

公开(公告)日：2013-03-12

申请号：US13290903

申请日：2011-11-07

申请人： Austin H. Lesea

发明人： Austin H. Lesea

IPC分类号： G06F17/50 ,  G06F11/00 ,  G01V3/00 ,  G01V7/00 ,  G01R31/28

CPC分类号： G06F17/5054 ,  G06F17/5081

摘要： In one embodiment, a method is provided for determining a level of resilience of a circuit to single event upsets based on a layout of a circuit design. A set of locations in the layout of the circuit design is selected. A respective maximum level of linear energy transfer (LET) that is tolerable for each location in the selected set is determined. For each determined maximum level of LET, cross-section values at locations having the maximum level of LET are summed to determine a respective total cross-section value for the maximum level of LET. For each determined maximum level of LET, the total cross-section value is divided by the determined maximum level of LET to produce respective intermediate values. The respective intermediate values are summed to determine a level of resilience.

摘要翻译： 在一个实施例中，提供了一种用于基于电路设计的布局来确定电路对单事件不匹配的弹性水平的方法。 选择电路设计布局中的一组位置。 确定对所选集合中的每个位置可容忍的相应的最大线性能量传递（LET）。 对于每个确定的LET的最大水平，将具有最大水平LET的位置处的横截面值相加以确定LET的最大水平的相应总横截面值。 对于每个确定的最大水平的LET，将总截面值除以确定的LET的最大水平以产生相应的中间值。 相应的中间值相加以确定弹性水平。

公开(公告)号：US08386990B1

公开(公告)日：2013-02-26

申请号：US12961753

申请日：2010-12-07

申请人： Stephen M. Trimberger ,  Austin H. Lesea

发明人： Stephen M. Trimberger ,  Austin H. Lesea

IPC分类号： G06F17/50 ,  G06F19/00 ,  H01L23/58 ,  H01L25/00 ,  H03K19/00

CPC分类号： G06F21/73 ,  H01L23/544 ,  H01L2223/5444 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/00

摘要： An embodiment of the invention relates to an integrated circuit such as an FPGA wherein a stable unique identifier is produced by reading an intrinsic characteristic of the IC such as a physically unclonable function, and a related method. In one embodiment, a first unique identifier is generated using the intrinsic characteristic and is subdivided into a plurality of first subsets. A second unique identifier is received and subdivided into a plurality of second subsets. The first and second subsets are compared to identify matching subsets to generate the stable unique identifier. Each of the one or more matching subsets includes a particular one of the plurality of first subsets that matches a corresponding one of the plurality of second subsets. The stable unique identifier can be integrated into logic of the IC. Prior to comparing the subsets, the first and second subsets can be transformed with one-way functions.

摘要翻译： 本发明的实施例涉及诸如FPGA的集成电路，其中通过读取诸如物理不可克隆功能的IC的固有特性来产生稳定的唯一标识符，以及相关方法。 在一个实施例中，使用本征特征生成第一唯一标识符，并将其细分为多个第一子集。 接收第二唯一标识符并将其细分成多个第二子集。 比较第一和第二子集以识别匹配子集以产生稳定的唯一标识符。 所述一个或多个匹配子集中的每一个包括与所述多个第二子集中的相应一个匹配的所述多个第一子集中的特定一个子集。 稳定的唯一标识符可以集成到IC的逻辑中。 在比较子集之前，第一和第二子集可以用单向函数进行变换。

公开(公告)号：US08117497B1

公开(公告)日：2012-02-14

申请号：US12247916

申请日：2008-11-17

申请人： Austin H. Lesea

发明人： Austin H. Lesea

IPC分类号： G06F11/00

CPC分类号： G06F11/10

摘要： A method and apparatus for the detection and correction of soft errors existing within an integrated circuit (IC). Run-time check stops are utilized in conjunction with processor-based, hardware mechanisms to detect and correct soft errors. At run-time, each check stop facilitates a snap shot of the hardware and/or software state of the IC to be stored into hardware and/or software based memory. Should a soft error be detected, execution is halted and the executable state of the IC that conforms to a previous check-stop location may be re-established after the soft error(s) are optionally corrected. In alternate embodiments, hardware based mechanisms may be exclusively utilized to both detect and correct the soft errors.

摘要翻译： 用于检测和校正存在于集成电路（IC）内的软错误的方法和装置。 运行时检查停止与基于处理器的硬件机制结合使用，以检测和纠正软错误。 在运行时，每个检查停止便于将要存储到硬件和/或基于软件的存储器中的IC的硬件和/或软件状态的快照。 如果检测到软错误，执行停止，并且可以在可选地校正软错误之后重新建立符合先前检查停止位置的IC的可执行状态。 在替代实施例中，基于硬件的机制可以专门用于检测和校正软错误。

公开(公告)号：US07944769B1

公开(公告)日：2011-05-17

申请号：US12579274

申请日：2009-10-14

申请人： Austin H. Lesea

发明人： Austin H. Lesea

IPC分类号： G11C5/14

CPC分类号： H03K3/02335

摘要： A system for detecting power-on of a circuit block within an integrated circuit (IC). The system can include a latch including a latch output and an inverted latch output. The latch can be coupled to, and powered by, a power supply providing power to the circuit block within the IC. The system further can include an exclusive OR circuit. The exclusive OR circuit can include an input stage coupled to the latch output and the inverted latch output. The exclusive OR circuit generates an output signal indicating whether the circuit block is in a power-on state.

摘要翻译： 一种用于检测集成电路（IC）内的电路块的通电的系统。 该系统可以包括具有锁存器输出和反相锁存器输出的锁存器。 锁存器可以耦合到由IC提供电力的电源并由其供电，该电源为IC内的电路块提供电力。 系统还可以包括异或电路。 异或电路可以包括耦合到锁存器输出和反相锁存器输出的输入级。 异或电路产生指示电路块是否处于通电状态的输出信号。