公开(公告)号：US4861418A

公开(公告)日：1989-08-29

申请号：US22402

申请日：1987-03-06

申请人： Tadashi Nishimura ,  Yasuo Inoue ,  Kazuyuki Sugahara ,  Shigeru Kusunoki

发明人： Tadashi Nishimura ,  Yasuo Inoue ,  Kazuyuki Sugahara ,  Shigeru Kusunoki

IPC分类号： H01L21/20 ,  H01L21/263 ,  H01L21/268 ,  H01L21/762 ,  H01L29/04

CPC分类号： H01L29/045 ,  H01L21/2026 ,  H01L21/268 ,  H01L21/76248 ,  Y10S117/904

摘要： A method of manufacturing a semiconductor crystalline layer comprising the following steps: a step of forming, on a single crystalline substrate composed of a semiconductor having a main face on face and having a diamond-type crystal structure, an orientation flat face in which the direction of the intersection with the main face makes a predetermined angle relative to the direction on the main face and which serves as a reference for defining the direction of arranging semiconductor chips formed on the substrate; a step of forming, on the main face of the substrate, an insulation layer at least a portion of which has an opening reaching the main face and which insulates the substrate at the region other than the opening; a step of forming a semiconductor layer composed of a polycrystalline or amorphous semiconductor on the surface of the opening and the insulation layer; a step of forming a reflectivity varying layer which is in the direction in parallel with or vertical to the intersection between the orientation flat face and the main face, has the width and the distance in a predetermined period and is set so as to show periodical reflectivity variation to the argon laser beams; and a step of scanning the argon laser beams under continuous irradiation by way of the reflectivity varying layer to the semiconductor layer in the direction identical with or at an angle within a certain permissible range to the direction of the main face or the direction equivalent thereto.

摘要翻译： 一种制造半导体结晶层的方法，包括以下步骤：在由具有主面的具有金刚石型晶体结构的半导体构成的单晶衬底上形成取向平面 其与主面的交点的方向相对于主面上的方向<110>成预定角度，并且作为用于限定形成在基板上的半导体芯片的排列方向的基准; 在所述基板的主面上形成绝缘层的步骤，所述绝缘层的至少一部分具有到达所述主面的开口，并且使所述基板与所述开口以外的区域绝缘; 在开口和绝缘层的表面上形成由多晶或非晶半导体构成的半导体层的步骤; 在与定向平面和主面之间的交叉部分平行或垂直的方向上形成反射率变化层的步骤具有在预定时间段内的宽度和距离，并且被设置为显示周期性反射率 对氩激光束的变化; 以及通过所述反射率变化层在与所述主面或所述主面的方向<110>的一定允许范围内相同或成一定角度的方向将所述氩激光束扫描到所述半导体层的步骤 相当于此。

公开(公告)号：US20070232564A1

公开(公告)日：2007-10-04

申请号：US11587789

申请日：2005-04-25

申请人： Kazuyuki Sugahara

发明人： Kazuyuki Sugahara

IPC分类号： A61K31/715 ,  A61P25/28

CPC分类号： C08B37/0069 ,  A61K31/715

摘要： It is intended to provide a novel chondroitin sulfate/dermatan sulfate hybrid chain having biding activity toward a variety of growth factors, neurite outgrowth-promoting activity, and anticoagulant activity and to provide a composition for neurological disease treatment. The novel chondroitin sulfate/dermatan sulfate hybrid chain was separated and purified from the bodies of fishes other than bony fishes. When shark skin is used, the hybrid chain comprises a disaccharide GlcUA(2S)-GalNAc(4S) and has an average molecular weight of 65 to 75 kDa, and the degree of sulfation per disaccharide molecule falls within the range of 0.7 or more to less than 1.20. The hybrid chain is capable of binding to a variety of growth factors and further possesses neurite outgrowth-promoting activity and anticoagulant activity.

摘要翻译： 本发明提供一种硫酸软骨素/硫酸皮肤素复合链，其具有针对各种生长因子，神经突促生长活性和抗凝血活性的粘合活性，并提供用于神经系统疾病治疗的组合物。 将硫酸软骨素/硫酸皮肤素杂交链从骨鱼以外的鱼体中分离纯化。 当使用鲨鱼皮时，杂交链包含二糖GlcUA（2S）-GalNAc（4S），平均分子量为65至75kDa，每个二糖分子的硫酸化程度在0.7以上至 小于1.20。 杂交链能够与多种生长因子结合，进一步具有神经突促生长活性和抗凝血活性。

公开(公告)号：US20070059805A1

公开(公告)日：2007-03-15

申请号：US11599371

申请日：2006-11-15

申请人： Kazuyuki Sugahara ,  Hiroshi Kitagawa

发明人： Kazuyuki Sugahara ,  Hiroshi Kitagawa

IPC分类号： C12P19/28

CPC分类号： C12N9/1051 ,  C12P19/26

摘要： A vector of the present invention has DNA encoding a protein or a product having the same effect as the protein, the protein containing an amino acid sequence from amino acid numbers 47 to 802 in SEQ. ID. NO:2. Expression of the DNA gives human chondroitin synthase. By using human chondroitin synthase, it is possible to produce a saccharide chain having a repeating disaccharide unit of chondroitin. The DNA or part thereof may be used as a probe for hybridization for the human chondroitin synthase.

摘要翻译： 本发明的载体具有编码蛋白质或具有与蛋白质相同效果的产物的DNA，该蛋白质含有SEQ ID NO：47至802的氨基酸序列。 ID。 NO：2。 DNA的表达给人类软骨素合成酶。 通过使用人软骨素合成酶，可以生成具有软骨素重复二糖单元的糖链。 DNA或其部分可以用作人类软骨素合酶杂交的探针。

公开(公告)号：US20050263770A1

公开(公告)日：2005-12-01

申请号：US11137660

申请日：2005-05-26

申请人： Kazuyuki Sugahara ,  Naoki Nakagawa ,  Yoshihiko Toyoda ,  Takao Sakamoto

发明人： Kazuyuki Sugahara ,  Naoki Nakagawa ,  Yoshihiko Toyoda ,  Takao Sakamoto

IPC分类号： H01L51/50 ,  H01L21/336 ,  H01L21/77 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/08 ,  H01L27/088 ,  H01L27/12 ,  H01L29/786 ,  H05B33/14

CPC分类号： H01L27/1222 ,  H01L27/1214 ,  H01L27/127 ,  H01L29/78621 ,  H01L29/78627

摘要： A first thin film transistor including a gate electrode, a source region, a drain region, a GOLD region, and a channel region is formed at a first region at a TFT array substrate. A second thin film transistor including a gate electrode, a source region, drain region, a GOLD region, and a channel region is formed at a second region. The GOLD length (0.5 μm) of the GOLD region of the second thin film transistor is set shorter than the GOLD length (1.5 μm) of the GOLD region of the first thin film transistor. Accordingly, a semiconductor device directed to reducing the area occupied by semiconductor elements is obtained.

摘要翻译： 在TFT阵列基板的第一区域形成包括栅极，源极区，漏极区，GOLD区和沟道区的第一薄膜晶体管。 在第二区域形成包括栅电极，源极区，漏极区，GOLD区和沟道区的第二薄膜晶体管。 第二薄膜晶体管的GOLD区域的GOLD长度（0.5μm）被设定为比第一薄膜晶体管的GOLD区域的GOLD长度（1.5μm）短。 因此，获得了旨在减小半导体元件所占的面积的半导体器件。

公开(公告)号：US20050253195A1

公开(公告)日：2005-11-17

申请号：US11109818

申请日：2005-04-20

申请人： Yoshihiko Toyoda ,  Takao Sakamoto ,  Kazuyuki Sugahara ,  Naoki Nakagawa

发明人： Yoshihiko Toyoda ,  Takao Sakamoto ,  Kazuyuki Sugahara ,  Naoki Nakagawa

IPC分类号： H01L27/08 ,  H01L21/00 ,  H01L21/336 ,  H01L21/77 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786

CPC分类号： H01L27/127 ,  H01L27/1214 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78645

摘要： A silicon nitride film and a silicon oxide film are formed on a glass substrate. On the silicon oxide film is formed a thin film transistor including a source region, a drain region, a channel region having a predetermined channel length, a GOLD region and an LDD region having an impurity concentration lower than the impurity concentration of the source region, a GOLD region and an LDD region having an impurity concentration lower than the impurity concentration of the drain region, a gate insulation film, and a gate electrode. The gate electrode is formed overlapping with and facing the channel region and the GOLD region. A semiconductor device is obtained, directed to improving source-drain breakdown voltage and AC stress resistance, and achieving desired current property.

摘要翻译： 在玻璃基板上形成氮化硅膜和氧化硅膜。 在氧化硅膜上形成薄膜晶体管，其包括源极区，漏极区，具有预定沟道长度的沟道区，GOLD区和具有低于源区杂质浓度的杂质浓度的LDD区， 具有杂质浓度低于漏区杂质浓度的GOLD区和LDD区，栅极绝缘膜和栅电极。 栅电极与沟道区域和金区域重叠并面对沟道区域。 获得了一种半导体器件，旨在改善源 - 漏击穿电压和AC抗应力，并实现期望的电流特性。

公开(公告)号：US20050236618A1

公开(公告)日：2005-10-27

申请号：US11091570

申请日：2005-03-29

申请人： Yoshihiko Toyoda ,  Takao Sakamoto ,  Kazuyuki Sugahara

发明人： Yoshihiko Toyoda ,  Takao Sakamoto ,  Kazuyuki Sugahara

IPC分类号： H01L27/08 ,  H01L21/336 ,  H01L21/77 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/12 ,  H01L29/786 ,  H01L31/113

CPC分类号： H01L27/1222 ,  H01L27/1214 ,  H01L27/127 ,  H01L29/66757 ,  H01L29/78624 ,  H01L2029/7863

摘要： A silicon nitride film and a silicon oxide film are formed on a glass substrate. On the silicon oxide film is formed a thin film transistor T including a source region, a drain region, a channel region having a predetermined channel length, a first GOLD region having an impurity concentration lower than the impurity concentration of the source region, a second GOLD region having an impurity concentration lower than the impurity concentration of the drain region, a gate insulation film, and a gate electrode. The length of an overlapping portion in plane between the gate electrode and the second GOLD region in the direction of the channel length is set longer than the length in the direction of the channel region of an overlapping portion in plane between the gate electrode and the first GOLD region.

摘要翻译： 在玻璃基板上形成氮化硅膜和氧化硅膜。 在氧化硅膜上形成薄膜晶体管T，该薄膜晶体管T包括源极区，漏极区，具有预定沟道长度的沟道区，具有低于源区杂质浓度的杂质浓度的第一GOLD区， GOLD区域的杂质浓度低于漏极区域的杂质浓度，栅极绝缘膜和栅电极。 在沟道长度方向上的栅电极和第二GOLD区之间的平面重叠部分的长度被设定为长于栅电极和第一栅极之间的平面重叠部分的沟道区域的方向上的长度 金地区。

公开(公告)号：US20050173763A1

公开(公告)日：2005-08-11

申请号：US11054384

申请日：2005-02-10

申请人： Toru Takeguchi ,  Kazuyuki Sugahara

发明人： Toru Takeguchi ,  Kazuyuki Sugahara

IPC分类号： H01L21/20 ,  H01L21/322 ,  H01L21/336 ,  H01L29/786 ,  H01L31/036

CPC分类号： H01L29/66757 ,  H01L29/66765 ,  H01L29/78621 ,  H01L29/78675

摘要： A semiconductor device includes a glass substrate having a main surface, a polysilicon film formed on the main surface, having a channel region formed and having a source region and a drain region formed on opposing sides of the channel region, a gate insulating film provided so as to be in contact with the polysilicon film and containing oxygen, and a gate electrode provided in a position facing the channel region with the gate insulating film being interposed. The polysilicon film has a thickness larger than 50 nm and not larger than 150 nm. The polysilicon film contains hydrogen in a proportion not smaller than 0.5 atomic percent and not larger than 10 atomic percent. With such a structure, a semiconductor device attaining a large drain current and having a desired electric characteristic is provided.

摘要翻译： 半导体器件包括具有主表面的玻璃衬底，形成在主表面上的多晶硅膜，具有形成的沟道区，并且具有形成在沟道区的相对侧上的源极区和漏极区，栅极绝缘膜设置为 与多晶硅膜接触并含有氧，以及设置在与栅极绝缘膜相对的沟道区的位置的栅电极。 多晶硅膜的厚度大于50nm且不大于150nm。 多晶硅膜含有不小于0.5原子％且不大于10原子％的比例的氢。 通过这样的结构，提供了获得大的漏极电流并具有期望的电特性的半导体器件。

公开(公告)号：US5446301A

公开(公告)日：1995-08-29

申请号：US274517

申请日：1994-07-13

申请人： Koji Eguchi ,  Natsuo Ajika ,  Kazuyuki Sugahara

发明人： Koji Eguchi ,  Natsuo Ajika ,  Kazuyuki Sugahara

IPC分类号： H01L21/20 ,  H01L21/336 ,  H01L21/768 ,  H01L21/84 ,  H01L27/06 ,  H01L27/12 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L27/01 ,  H01L29/06

CPC分类号： H01L29/66772 ,  H01L27/0688 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/78654

摘要： A semiconductor device capable of effectively preventing a dielectric breakdown of a gate oxide film without adversely affecting the characteristics of a transistor and a process of manufacturing the same are disclosed. The semiconductor device comprises a SOI film 2 whose upper angular parts are rounded off by sputter etching and a gate oxide film 3 formed on SOI film 2 with an almost uniform thickness. Therefore, electric field concentration in the upper angular parts of SOI film 2 is reduced. Furthermore, the control characteristics of the transistor are enhanced by the uniform gate oxide film 3. As a result, a dielectric breakdown of the gate oxide film is effectively prevented without adversely affecting the characteristics of the transistor. Sputter etching enabling processing at a low temperature is used, so that the upper angular parts of SOI film 2 are rounded off without adversely affecting a semiconductor element formed in the lower layer.

摘要翻译： 公开了能够有效地防止栅极氧化膜的介电击穿而不会不利地影响晶体管的特性的半导体器件及其制造方法。 该半导体器件包括通过溅射蚀刻使上角部分被倒圆的SOI膜2和形成在具有几乎均匀厚度的SOI膜2上的栅极氧化膜3。 因此，SOI膜2的上角部的电场浓度降低。 此外，通过均匀的栅极氧化膜3增强晶体管的控制特性。结果，有效地防止了栅极氧化膜的电介质击穿，而不会不利地影响晶体管的特性。 使用能够在低温下进行的溅射蚀刻，使得SOI膜2的上角部分被倒圆而不会对形成在下层中的半导体元件产生不利影响。

公开(公告)号：US5381029A

公开(公告)日：1995-01-10

申请号：US838993

申请日：1992-02-21

申请人： Koji Eguchi ,  Natsuo Ajika ,  Kazuyuki Sugahara

发明人： Koji Eguchi ,  Natsuo Ajika ,  Kazuyuki Sugahara

IPC分类号： H01L21/20 ,  H01L21/336 ,  H01L21/768 ,  H01L21/84 ,  H01L27/06 ,  H01L27/12 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L27/01 ,  H01L29/06

CPC分类号： H01L29/66772 ,  H01L27/0688 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/78654

摘要： A semiconductor device capable of effectively preventing a dielectric breakdown of a gate oxide film without adversely affecting the characteristics of a transistor and a process of manufacturing the same are disclosed. The semiconductor device comprises a SOI film 2 whose upper angular parts are rounded off by sputter etching and a gate oxide film 3 formed on SOI film 2 with an almost uniform thickness. Therefore, electric field concentration in the upper angular parts of SOI film 2 is reduced. Furthermore, the control characteristics of the transistor are enhanced by the uniform gate oxide film 3. As a result, a dielectric breakdown of the gate oxide film is effectively prevented without adversely affecting the characteristics of the transistor. Sputter etching enabling processing at a low temperature is used, so that the upper angular parts of SOI film 2 are rounded off without adversely affecting a semiconductor element formed in the lower layer.

公开(公告)号：US5315140A

公开(公告)日：1994-05-24

申请号：US8020

申请日：1993-01-22

申请人： Kazuyuki Sugahara ,  Hideaki Arima

发明人： Kazuyuki Sugahara ,  Hideaki Arima

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/16 ,  H01L29/94

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/91 ,  H01L29/16 ,  H01L29/94

摘要： A semiconductor device includes a capacitor with an insulator having an improved durability. In the semiconductor device, a capacitor lower electrode 11 of the cylindrical capacitor includes a standing wall portion 11b which is formed of a polysilicon layer having a large crystal grain diameter (1000.ANG.-10000.ANG.).

摘要翻译： 半导体器件包括具有改善的耐久性的具有绝缘体的电容器。 在半导体装置中，圆筒形电容器的电容器下电极11包括由具有大晶粒直径（1000安格姆-10000昂贵）的多晶硅层形成的立壁部分11b。