公开(公告)号：US06542013B1

公开(公告)日：2003-04-01

申请号：US10037915

申请日：2002-01-02

申请人： Andrew M. Volk ,  Ronald W. Swartz

发明人： Andrew M. Volk ,  Ronald W. Swartz

IPC分类号： H03K2100

CPC分类号： H03L7/1974 ,  H03K23/68 ,  H03L7/0996

摘要： A frequency multiplier is described for synthesizing frequencies. The frequency multiplier includes a phase locked loop (PLL) circuit having an oscillator to generate a number of phase signals and a phase-shifting circuit coupled to the PLL circuit to select one of the phase signals generated by the oscillator according to a defined phase sequence to be passed to a feedback loop. Also included in the frequency multiplier is a divide-by-M circuit inserted in the feedback loop which divides a frequency of the signal selected by the phase-shifting circuit to generate a feedback signal for the PLL circuit. In one embodiment, the feedback signal generated by the divide-by-M circuit serves as a control signal to enable the phase-shifting circuit.

摘要翻译： 描述了用于合成频率的倍频器。 倍频器包括具有产生多个相位信号的振荡器的锁相环（PLL）电路和耦合到PLL电路的相移电路，以根据定义的相序选择由振荡器产生的相位信号之一 被传递给一个反馈回路。 倍频器中还包括插入在反馈环路中的除M电路，其分频由移相电路选择的信号的频率以产生用于PLL电路的反馈信号。 在一个实施例中，由M分频电路产生的反馈信号用作控制信号以使能移相电路。

公开(公告)号：US06516396B1

公开(公告)日：2003-02-04

申请号：US09470300

申请日：1999-12-22

申请人： Andrew M. Volk ,  Puthiya K. Nizar

发明人： Andrew M. Volk ,  Puthiya K. Nizar

IPC分类号： G06F1200

CPC分类号： G06F13/1689

摘要： A method and system for extending tTR range of memory devices coupled to a memory devices is described. A first group of memory devices and a second group of memory devices are identified. The first group includes memory devices located close to a memory controller and the second group includes memory devices located a distance away from the memory controller. Commands to access memory devices in the first and second groups are sent. A command to the first group is sent with a transitional delay when the command to the first group follows a command to the second group. In response to the commands, data from the first and second groups is received.

摘要翻译： 描述了用于扩展耦合到存储器件的存储器件的tTR范围的方法和系统。 识别第一组存储器件和第二组存储器件。 第一组包括位于存储器控制器附近的存储器件，第二组包括距离存储器控制器一定距离的存储器件。 发送访问第一组和第二组中的存储设备的命令。 当对第一组的命令遵循对第二组的命令时，向第一组发送的命令具有过渡延迟。 响应于这些命令，接收来自第一组和第二组的数据。

公开(公告)号：US06356105B1

公开(公告)日：2002-03-12

申请号：US09606846

申请日：2000-06-28

申请人： Andrew M. Volk

发明人： Andrew M. Volk

IPC分类号： H03K1716

CPC分类号： H03K19/0005 ,  H03K19/00361

摘要： A method and apparatus for an impedance control system for a center tapped termination bus. One method of the present invention comprises comparing an output potential of a buffer with a pair of reference potentials. The output impedance of the buffer is adjusted to cause the buffer output voltage swing to match the reference potentials.

摘要翻译： 一种用于中央抽头终端总线的阻抗控制系统的方法和装置。 本发明的一种方法包括将缓冲器的输出电位与一对参考电位进行比较。 调整缓冲器的输出阻抗，使缓冲器输出电压摆幅与参考电位相匹配。

公开(公告)号：US06191662B1

公开(公告)日：2001-02-20

申请号：US09452048

申请日：1999-11-30

申请人： Andrew M. Volk

发明人： Andrew M. Volk

IPC分类号： H03B506

CPC分类号： H03K3/3545 ,  H03K3/014 ,  H03K3/0307

摘要： A clock circuit includes an oscillator having a biasing node that causes the oscillator to enter a low-power state. The clock circuit also includes a kick-start circuit and a first mechanism. The kick-start circuit operates to provide an excitation to the oscillator, where the excitation enables the oscillator to start its oscillation. The first mechanism is configured to inhibit kick-start based on certain conditions, such as when the oscillator reaches a particular level capable of sustaining oscillation by itself or when the oscillator is already running.

摘要翻译： 时钟电路包括具有使振荡器进入低功率状态的偏置节点的振荡器。 时钟电路还包括启动电路和第一机构。 启动电路用于向振荡器提供激励，其中激励使振荡器能够开始其振荡。 第一机构被配置为基于某些条件来禁止启动启动，例如当振荡器达到能够自身维持振荡的特定电平时或当振荡器已经在运行时。

公开(公告)号：US6128749A

公开(公告)日：2000-10-03

申请号：US186046

申请日：1998-11-03

申请人： David J. McDonnell ,  Andrew M. Volk ,  Michael W. Williams

发明人： David J. McDonnell ,  Andrew M. Volk ,  Michael W. Williams

IPC分类号： G06F1/04 ,  G06F12/00 ,  G06F13/00 ,  H04L12/403 ,  H04L12/54

CPC分类号： G06F5/06 ,  G06F13/1689 ,  G06F2205/061

摘要： An apparatus and method for transferring units of information between clock domains. A respective set of N units of information is loaded from an output circuit in a first clock domain into a storage circuit in a second clock domain during each cycle of the first clock domain. Each set of N units is selected by the output circuit to include (1) units of information that have previously been loaded into the storage circuit and that will not be output from the storage circuit prior to the storage circuit being loaded with a subsequent set of N units of information, and (2) a complement number of units of information that have not previously been loaded into the storage circuit.

摘要翻译： 一种用于在时钟域之间传送信息单元的装置和方法。 在第一时钟域的每个周期期间，将相应的N个信息单元从第一时钟域中的输出电路加载到第二时钟域中的存储电路中。 每一组N个单元由输出电路选择，包括（1）先前已经被加载到存储电路中的信息单元，并且在存储电路装载下一组 N个信息单元，以及（2）尚未加载到存储电路中的补充信息单元。

公开(公告)号：US6128359A

公开(公告)日：2000-10-03

申请号：US181034

申请日：1998-10-27

申请人： Andrew M. Volk

发明人： Andrew M. Volk

IPC分类号： G06F1/10 ,  H03D13/00 ,  H03L7/081 ,  H03L7/087 ,  H04L7/00

CPC分类号： H03L7/0812 ,  G06F1/10 ,  H03D13/004 ,  H03L7/087

摘要： An apparatus and method for indicating a phase difference between a first input signal and a second input signal. A first delayed signal is generated by delaying a reference signal for a first predetermined time and a second delayed signal is generated by delaying the reference signal for a second predetermined time, the second predetermined time being longer than the first predetermined time. The leading signal of the first and second input signals is detected. If the first input signal leads the second input signal, the first delayed signal is output to represent the first input signal and a signal that lags the first delayed signal by a third predetermined time is output to represent the second input signal. If the second input signal leads the first input signal, the second delayed signal is output to represent the first input signal and a signal that leads the second delayed signal by a fourth predetermined time is output to represent the second input signal.

摘要翻译： 一种用于指示第一输入信号和第二输入信号之间的相位差的装置和方法。 通过在第一预定时间内延迟参考信号来产生第一延迟信号，并且通过将参考信号延迟第二预定时间而产生第二延迟信号，第二预定时间长于第一预定时间。 检测第一和第二输入信号的前导信号。 如果第一输入信号引导第二输入信号，则输出第一延迟信号以表示第一输入信号，并输出延迟第一延迟信号第三预定时间的信号以表示第二输入信号。 如果第二输入信号引导第一输入信号，则输出第二延迟信号以表示第一输入信号，并输出引导第二延迟信号第四预定时间的信号以表示第二输入信号。

公开(公告)号：US6112306A

公开(公告)日：2000-08-29

申请号：US167507

申请日：1998-10-06

申请人： Andrew M. Volk ,  Michael W. Williams

发明人： Andrew M. Volk ,  Michael W. Williams

IPC分类号： G06F1/32 ,  G11C7/10 ,  G11C7/22

CPC分类号： G06F1/3225 ,  G11C7/1039 ,  G11C7/22

摘要： A self-synchronizing method and apparatus for exiting a dynamic random access memory from a low power state is provided. The exit from the low power state is initiated. After the expiration of an exit delay period, a first quiet time is sent on a column-access pin. A second quiet time is sent on a row-access pins to reset the memory. The first quiet time and the second quiet time are not necessarily concurrent.

摘要翻译： 提供了一种用于从低功率状态退出动态随机存取存储器的自同步方法和装置。 启动从低功率状态的退出。 退出延迟时间到期后，在列访问引脚上发送第一个安静时间。 在行访问引脚上发送第二个安静的时间以重置内存。 第一个安静的时间和第二个安静的时间并不一定是并行的。

公开(公告)号：US5332930A

公开(公告)日：1994-07-26

申请号：US82280

申请日：1993-06-24

申请人： Andrew M. Volk

发明人： Andrew M. Volk

IPC分类号： H03L1/00 ,  H03L7/089 ,  H03L7/093 ,  H03L7/16 ,  H03L7/08

CPC分类号： H03L1/00 ,  H03L7/0893 ,  H03L7/093

摘要： An adjustable current source circuit of a phase locked loop (PLL) circuitry fabricated on a single substrate provides a first current that is a function of an error voltage proportional to an amount of a phase difference of a comparison of a reference signal and a feedback signal. The circuit includes a first current source coupled to receive a second current from a reference phase locked loop of the PLL circuitry for providing a first portion of the first current under control of the second current. The first portion of the first current is proportional to the second current. A second current source is coupled to receive a third current from a transconductance amplifier of the PLL circuitry for providing a second portion of the first current under control of the third current. The second portion of the first current is proportional to the third current. A third current source provides a third portion of the first current selectively proportional to one of the second and third currents. A switching circuit is coupled to receive the second and third currents for selectively controlling the third current source to couple to one of the second and third currents in order to cause the third portion of the first current proportional to the selected one of the second and third currents such that the first current can be switched to have one of a first current ratio and a second current ratio between the second and third currents and therefore the PLL circuitry can be switched between a first and a second bandwidth and loop gain.

摘要翻译： 制造在单个基板上的锁相环（PLL）电路的可调电流源电路提供第一电流，其是与参考信号和反馈信号的比较的相位差成比例的误差电压的函数 。 电路包括耦合以从PLL电路的参考锁相环接收第二电流的第一电流源，用于在第二电流的控制下提供第一电流的第一部分。 第一电流的第一部分与第二电流成比例。 耦合第二电流源以从PLL电路的跨导放大器接收第三电流，以在第三电流的控制下提供第一电流的第二部分。 第一电流的第二部分与第三电流成比例。 第三电流源提供选择性地与第二和第三电流之一成比例的第一电流的第三部分。 开关电路被耦合以接收第二和第三电流，用于选择性地控制第三电流源以耦合到第二和第三电流中的一个，以便使第一电流的第三部分与第二和第三电流中选定的一个成比例 电流，使得第一电流可以被切换成具有第二和第三电流之间的第一电流比和第二电流比之一，因此PLL电路可以在第一和第二带宽和环路增益之间切换。

公开(公告)号：US4819081A

公开(公告)日：1989-04-04

申请号：US92477

申请日：1987-09-03

申请人： Andrew M. Volk ,  Terry L. Baucom ,  Roger Van Brunt

发明人： Andrew M. Volk ,  Terry L. Baucom ,  Roger Van Brunt

IPC分类号： H03D13/00 ,  H03L7/10 ,  H03D3/02

CPC分类号： H03L7/10 ,  H03D13/004

摘要： An extended range logic circuit is activated to decrease the settling time and prevent slip, when phase difference of two signals being compared by a phase comparator reaches a slip point. The circuit provides error correction signals to compensate for the phase correction at a much faster rate when the phase error reaches a predetermined point, which is proximate to the slip point. However, the extended capture range circuit in only active during the lock acquisition. After lock is achieved the extended capture range logic is disabled, to provide better jitter performance.

摘要翻译： 当相位比较器比较两个信号的相位差达到滑点时，扩展范围逻辑电路被激活以减小建立时间并防止滑动。 当相位误差达到接近滑点的预定点时，电路提供纠错信号以更快的速率补偿相位校正。 但是，扩展捕捉范围电路只在锁定采集期间有效。 实现锁定后，扩展捕获范围逻辑被禁用，以提供更好的抖动性能。

公开(公告)号：US20080162062A1

公开(公告)日：2008-07-03

申请号：US11648488

申请日：2006-12-28

申请人： Mukul Kelkar ,  Andrew M. Volk ,  Rajesh Kanakath ,  Vui Y. Liew

发明人： Mukul Kelkar ,  Andrew M. Volk ,  Rajesh Kanakath ,  Vui Y. Liew

IPC分类号： G01R29/02 ,  G01F15/06

CPC分类号： G01R31/31727

摘要： In some embodiments, a chip includes clock generation circuitry to create a clock signal, and reference signal oscillator circuitry to produce a reference signal with a higher frequency than the clock signal. The chip includes a counter to change a count value in response to changes in the reference signal; and count logic circuitry to cause count storage circuitry to read the count value in response to at least some changes in the clock signal and to make at least some of the values in the count storage circuitry related to a duty cycle of the clock signal available to an external tester. Other embodiments are described and claimed.

摘要翻译： 在一些实施例中，芯片包括用于产生时钟信号的时钟产生电路和参考信号振荡器电路，以产生具有比时钟信号更高的频率的参考信号。 芯片包括响应于参考信号变化而改变计数值的计数器; 以及计数逻辑电路，以使得计数存储电路响应于所述时钟信号中的至少一些变化来读取所述计数值，并且使所述计数存储电路中的至少一些值与所述时钟信号的占空比相关， 外部测试仪 描述和要求保护其他实施例。