公开(公告)号：US09653152B1

公开(公告)日：2017-05-16

申请号：US15352197

申请日：2016-11-15

Applicant: QUALCOMM Incorporated

Inventor： Tony Chung Yiu Kwok ,  Changho Jung

IPC: G06F12/00 ,  G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G06F13/1668 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/418 ,  G11C2207/2209

Abstract: In an aspect of the disclosure, an apparatus is provided. In one aspect, the apparatus is a memory controller that includes a logic circuit configured to generate a select signal for selecting between first and second ports of a memory as a function of first and second port signals. Additionally, the memory controller includes a switch configured to connect and disconnect the first and the second port signals. In another aspect of the disclosure, the apparatus is a storage apparatus that includes a memory and a memory controller. The memory controller includes a latch configured to latch a first port selection signal to produce a first port signal and latch a second port selection signal to produce a second port signal. The memory controller also includes a switch configured to connect and disconnect the first and the second port signals and a logic circuit configured to generate a select signal.

公开(公告)号：US09536578B2

公开(公告)日：2017-01-03

申请号：US13863989

申请日：2013-04-16

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Changho Jung ,  Sei Seung Yoon ,  Rakesh Vattikonda ,  Nishith Desai

IPC: G11C7/12 ,  G11C7/10 ,  G11C11/419

CPC classification number: G11C7/12 ,  G11C7/1084 ,  G11C7/1096 ,  G11C11/419

Abstract: A write driver for a memory circuit includes a control circuit configured to: operate a first push-pull driver to generate a first drive signal in a first voltage domain at a first node based on an input signal in a second domain and in response to a mode select signal being in a first mode, wherein the first drive signal is at a same logic level as the input signal; operate a second push-pull driver to generate a second drive signal in the first voltage domain at a second node based on the input signal and in response to the mode select signal being in the first mode, wherein the second drive signal is at a complement logic level with respect to the input signal; and operate the first and second push-pull drivers to float the first and second nodes in response to the mode select signal being in a second mode.

Abstract translation: 用于存储器电路的写驱动器包括控制电路，该控制电路被配置为：基于第二域中的输入信号，并响应于第一推挽驱动器响应于第一推挽驱动器，在第一节点处的第一电压域中产生第一驱动信号 模式选择信号处于第一模式，其中第一驱动信号处于与输入信号相同的逻辑电平; 操作第二推挽驱动器以基于输入信号在第二节点处的第一电压域中产生第二驱动信号，并且响应于模式选择信号处于第一模式，其中第二驱动信号为补码 相对于输入信号的逻辑电平; 并且响应于所述模式选择信号处于第二模式，操作所述第一和第二推挽驱动器使所述第一和第二节点浮动。

公开(公告)号：US20160372167A1

公开(公告)日：2016-12-22

申请号：US14745216

申请日：2015-06-19

Applicant: QUALCOMM Incorporated

Inventor： Nishith Nitin Desai ,  Tony Chung Yiu Kwok ,  Changho Jung

IPC: G11C7/12 ,  G11C11/419

CPC classification number: G11C7/12 ,  G11C7/08 ,  G11C11/419 ,  G11C2207/002

Abstract: A pseudo-dual-port (PDP) memory such as a PDP SRAM is provided that independently controls the bit line precharging and the sense amplifier precharging to increase memory operating speed while eliminating or reducing the discharge of crowbar current.

Abstract translation: 提供诸如PDP SRAM的伪双端口（PDP）存储器，其独立地控制位线预充电和感测放大器预充电以增加存储器操作速度，同时消除或减少撬棒电流的放电。

公开(公告)号：US09324416B2

公开(公告)日：2016-04-26

申请号：US14464627

申请日：2014-08-20

Applicant: QUALCOMM Incorporated

Inventor： Sei Seung Yoon ,  Tony Chung Yiu Kwok ,  Changho Jung ,  Nishith Nitin Desai

IPC: G11C16/04 ,  G11C11/419 ,  G11C7/10 ,  G11C7/22

CPC classification number: G11C11/419 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/1075 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222 ,  G11C8/16 ,  G11C11/412

Abstract: A memory and a method for operating the memory provided. In one aspect, the memory may be a PDP memory. The memory includes a control circuit configured to generate a first clock and a second clock in response an edge of a clock for an access cycle. A first input circuit is configured to receive an input for a first memory access based on the first clock. The first input circuit includes a latch. The second input circuit configured to receive an input for a second memory access based on the second clock. The second input circuit includes a flip-flop.

Abstract translation: 用于操作所提供的存储器的存储器和方法。 在一个方面，存储器可以是PDP存储器。 存储器包括控制电路，该控制电路经配置以响应于访问周期的时钟的边沿而产生第一时钟和第二时钟。 第一输入电路被配置为基于第一时钟接收用于第一存储器访问的输入。 第一输入电路包括锁存器。 第二输入电路被配置为基于第二时钟接收用于第二存储器访问的输入。 第二输入电路包括触发器。

公开(公告)号：US20150303921A1

公开(公告)日：2015-10-22

申请号：US14257212

申请日：2014-04-21

Applicant: QUALCOMM Incorporated

Inventor： Changho Jung ,  Frank Guo ,  Rakesh Vattikonda

IPC: H03K19/0185

CPC classification number: H03K19/018521 ,  H03K3/356182

Abstract: A level-shifter is provided with PMOS stacks that are selectively weakened or strengthened depending upon the binary state of an input signal.

Abstract translation: 电平移位器具有根据输入信号的二进制状态选择性地削弱或加强的PMOS堆叠。

公开(公告)号：US08976607B2

公开(公告)日：2015-03-10

申请号：US13784830

申请日：2013-03-05

Applicant: QUALCOMM Incorporated

Inventor： Nishith Desai ,  Rakesh Vattikonda ,  Changho Jung

IPC: G11C16/04 ,  G11C7/10 ,  G11C11/417 ,  G11C7/22

CPC classification number: G11C7/1096 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/22 ,  G11C11/417 ,  G11C2207/2227

Abstract: Various aspects of a fast, energy efficient write driver capable of efficient operation in a dual-voltage domain memory architecture are provided herein. Specifically, various aspects of the write driver described herein combine a high speed driver with voltage level shifting capabilities that may be implemented efficiently in reducing use of silicon area while using lower power. The write driver circuit shifts or adjusts voltage levels between a first voltage domain to a second voltage domain. In one example, the write driver circuit is coupled to a global write bitline and a local write bitline that is coupled to one or more bitcells (of SRAM memory). The write driver circuit converts a first voltage level at the global write bitline to a second voltage level at the local write bitline during a write operation.

Abstract translation: 本文提供了能够在双电压域存储器架构中有效操作的快速，高能量写入驱动器的各个方面。 具体来说，这里描述的写入驱动器的各个方面将高速驱动器与电压电平转换能力相结合，可以在减少使用较低功耗的硅片区域的同时有效地实现。 写驱动器电路移位或调整第一电压域与第二电压域之间的电压电平。 在一个示例中，写驱动器电路耦合到耦合到SRAM存储器的一个或多个位单元的全局写位线和本地写位线。 写入驱动器电路在写操作期间将全局写位线处的第一电压电平转换为本地写位线处的第二电压电平。

公开(公告)号：US08971096B2

公开(公告)日：2015-03-03

申请号：US13953473

申请日：2013-07-29

Applicant: QUALCOMM Incorporated

Inventor： Changho Jung ,  Rakesh Vattikonda ,  Nishith Desai ,  Sei Seung Yoon

IPC: G11C11/00 ,  G11C11/419

CPC classification number: G11C11/419 ,  G11C8/16

Abstract: A multiport bitcell including a pair of cross-coupled inverters is provided with increased write speed and enhanced operating voltage range by the selective isolation of a first one of the cross-coupled inverters from a power supply and ground during a write operation. The write operation occurs through a write port that includes a transmission gate configured to couple a first node driven by the first cross-coupled inverter to a write bit line. A remaining second cross-coupled inverter in the bitcell is configured to drive a second node that couples to a plurality of read ports.

Abstract translation: 包括一对交叉耦合的反相器的多端口位单元通过在写入操作期间从电源和接地中选择性隔离交叉耦合的反相器中的第一个而提供增加的写入速度和增强的工作电压范围。 写入操作通过写入端口发生，该写入端口包括被配置为将由第一交叉耦合的反相器驱动的第一节点耦合到写入位线的传输门极。 位单元中的剩余的第二交叉耦合反相器被配置为驱动耦合到多个读端口的第二节点。

公开(公告)号：US20140253201A1

公开(公告)日：2014-09-11

申请号：US13787530

申请日：2013-03-06

Applicant: QUALCOMM INCORPORATED

Inventor： Changho Jung ,  Nishith Desai ,  Rakesh Vattikonda

IPC: H03K3/012 ,  H03K3/011

CPC classification number: H03K3/356104

Abstract: Various apparatuses and methods are disclosed. The system describes a pulse generator comprising a first stage configured to be powered by a first voltage; and a second stage configured to be powered by a second voltage different from the first voltage, wherein the second stage is further configured to generate a pulse in response to an input to the first stage comprising a trigger and feedback from the second stage.

Abstract translation: 公开了各种装置和方法。 该系统描述了脉冲发生器，其包括被配置为由第一电压供电的第一级; 以及第二级，其被配置为由不同于所述第一电压的第二电压供电，其中所述第二级还被配置为响应于包括来自所述第二级的触发和来自所述第一级的输入而产生脉冲。

公开(公告)号：US20140198598A1

公开(公告)日：2014-07-17

申请号：US13741886

申请日：2013-01-15

Applicant: QUALCOMM INCORPORATED

Inventor： Changho Jung ,  Peng Jin ,  Sei Seung Yoon

IPC: G11C5/14

CPC classification number: G11C5/14 ,  G11C5/148 ,  G11C8/10

Abstract: The disclosure relates to an apparatus for deactivating one or more predecoded address lines of a memory circuit in response to one or more of the predecoded address lines being activated upon powering on of at least a portion of the apparatus. In particular, the apparatus includes a memory device; an address predecoder configured to activate one or more of a plurality of predecoded address lines based on an input address, wherein the plurality of predecoded address lines are coupled to the memory device for accessing one or more memory cells associated with the one or more activated predecoded address lines; and a power-on-reset circuit configured to deactivate one or more of the predecoded address lines in response to the one or more of the predecoded address lines being activated upon powering on the at least portion of the apparatus.

Abstract translation: 本公开涉及一种用于响应于一个或多个预解码地址线在对设备的至少一部分通电而被激活而停用存储器电路的一个或多个预解码地址线的装置。 具体地，该装置包括存储装置; 地址预解码器，被配置为基于输入地址激活多个预解码地址线中的一个或多个，其中所述多个预解码地址线耦合到所述存储器设备，用于访问与所述一个或多个激活的预解码的相关联的一个或多个存储器单元 地址线 以及上电复位电路，其被配置为响应于在对所述装置的所述至少一部分供电上启动的所述预解码地址线中的一个或多个来停用所述预解码地址线中的一个或多个。

公开(公告)号：US20130223178A1

公开(公告)日：2013-08-29

申请号：US13663042

申请日：2012-10-29

Applicant: QUALCOMM Incorporated

Inventor： Esin Terzioglu ,  Changho Jung ,  Shahzad Nazar ,  Balachander Ganesan ,  Alex Dongkyu Park

IPC: G11C8/10

CPC classification number: G11C8/10

Abstract: A global reset generation method for a pulse latch based pre-decoders in memories that comprises generating a pre-decoded memory address output for a pulse latch circuit, generating a reset signal to reset the pulse latch circuit, providing a combined signal of the pre-decoded memory address output and the reset signal, feeding the combined signal into a low voltage threshold device to manipulate resetting the pulse latch circuit, wherein generating a reset signal comprises generating a reset signal from a matched circuit that is configured to mimic the function of the latch circuit to be reset and wherein generating a reset signal comprises configuring the matched circuit to accommodate a worst case hold pulse delay to allow for resetting the pulse latch before a new clock cycle performs the resetting and having the matched circuit provide the reset signal and a pre-decoded memory address output in the same voltage domain.

Abstract translation: 一种用于存储器中基于脉冲锁存器的预解码器的全局复位产生方法，包括产生用于脉冲锁存电路的预解码存储器地址输出，产生复位信号以复位脉冲锁存电路，提供预处理器的组合信号， 解码的存储器地址输出和复位信号，将组合的信号馈送到低电压阈值器件以操纵复位脉冲锁存电路，其中产生复位信号包括产生来自匹配电路的复位信号，该匹配电路被配置为模拟 锁存电路被复位并且其中产生复位信号包括配置匹配电路以适应最坏情况保持脉冲延迟，以允许在新的时钟周期执行复位之前复位脉冲锁存器并使匹配电路提供复位信号和 在同一电压域内预编译的存储器地址输出。