公开(公告)号：US20190305077A1

公开(公告)日：2019-10-03

申请号：US15937097

申请日：2018-03-27

Applicant: QUALCOMM Incorporated

Inventor： Peijie FENG ,  Junjing BAO ,  Ye LU ,  Giridhar NALLAPATI

IPC: H01L49/02 ,  H01L23/522

Abstract: A capacitor includes first conductive fingers interdigitated with second conductive fingers at an Mx interconnect level, and third conductive fingers interdigitated with fourth conductive fingers at an Mx-1 interconnect level. The third conductive fingers are offset from the first conductive fingers. The second conductive fingers are offset from the fourth conductive fingers. The capacitor further includes fifth conductive fingers interdigitated with sixth conductive fingers at an Mx-2 interconnect level. The fifth conductive fingers are offset from the third conductive fingers. The sixth conductive fingers are offset from the fourth conductive fingers. The capacitor further includes seventh conductive fingers interdigitated with eighth conductive fingers at an Mx-3 interconnect level. The seventh conductive fingers are offset from the fifth conductive fingers. The eighth conductive fingers are offset from the sixth conductive fingers. A first set of vias electrically couples the first conductive fingers to the fifth conductive fingers.

公开(公告)号：US20250107157A1

公开(公告)日：2025-03-27

申请号：US18475053

申请日：2023-09-26

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Junjing BAO ,  Biswa Ranjan PANDA

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: An electronic device having one or more Gate-All-Around GAA transistors is disclosed. At least one of the one or more GAA transistors comprises one or more inner gate structures having a work function metal bounded by a gate dielectric; and one or more inner gate spacers associated with the one or more inner gate structures, wherein each of the one or more inner gate structures has a generally concave outer edge that conforms to a generally convex inner edge of an associated inner gate spacer of the one or more inner gate spacers.

公开(公告)号：US20240404872A1

公开(公告)日：2024-12-05

申请号：US18327786

申请日：2023-06-01

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  Haining YANG ,  Ming-Huei LIN

IPC: H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/532 ,  H01L27/088 ,  H01L29/06

Abstract: Disclosed are devices that include a direct N/P local interconnect with minimal recess on shallow trench isolation (STI) oxide. This reduces undesirable coupling capacitance with active gate, which in turn improves AC performance of the device. Pull or even partial replacement of STI oxide with low-k dielectric can further reduce coupling capacitance.

公开(公告)号：US20240297218A1

公开(公告)日：2024-09-05

申请号：US18178248

申请日：2023-03-03

Applicant: QUALCOMM Incorporated

Inventor： Kwanyong LIM ,  Hyunwoo PARK ,  Junjing BAO ,  Haining YANG

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/78696

Abstract: Disclosed are techniques for a semiconductor structure. In an aspect, a semiconductor structure includes a first gate structure disposed on a substrate and having a first channel length; a second gate structure disposed on the substrate and having the first channel length, a first source/drain space between the first gate structure and the second gate structure having a first distance; a third gate structure disposed on the substrate and having a second channel length; and a fourth gate structure disposed on the substrate and having the second channel length, a second source/drain space between the third gate structure and the fourth gate structure having a second distance. In an aspect, the second distance ranges from 0.75 times to 1.25 times the first distance.

公开(公告)号：US20230008615A1

公开(公告)日：2023-01-12

申请号：US17369532

申请日：2021-07-07

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Bin YANG ,  Junjing BAO

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/24 ,  H01L27/092 ,  H01L29/66

Abstract: Disclosed are semiconductor devices including a double gate metal oxide semiconductor (MOS) transistor and methods for fabricating the same. The double gate MOS transistor includes a first back gate, a second back gate, and a first dielectric layer disposed on the first back gate and on the second back gate. An MX2 material layer is disposed on the first dielectric layer, a second dielectric layer disposed on the MX2 material layer, and a work function metal (WFM) is disposed on the second dielectric layer. A front gate is disposed on the WFM, which fills a space between the first back gate and the second back.

公开(公告)号：US20220336351A1

公开(公告)日：2022-10-20

申请号：US17234377

申请日：2021-04-19

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong ZHU ,  Junjing BAO ,  Giridhar NALLAPATI

IPC: H01L23/528 ,  H01L23/522 ,  H01L25/18 ,  H01L21/768

Abstract: In an aspect, a system on a chip (SOC) includes a plurality of function blocks, including a first function block and a second function block, co-located on the SOC. The SOC includes a first metal layer, a first dielectric layer located on top of the first metal layer, and a first via located in the first dielectric layer and used in the first function block. The SOC includes a second via located in the first dielectric layer and used in the second function block and a second metal layer located on the first dielectric layer. The second metal layer comprises a first set of connections used in the first function block and a second set of connections used in the second function block. The first set of connections is different from the second set of connections. The SOC includes a second dielectric layer located on the first dielectric layer.

公开(公告)号：US20220109053A1

公开(公告)日：2022-04-07

申请号：US17061709

申请日：2020-10-02

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  Jun YUAN ,  Peijie FENG

IPC: H01L29/417 ,  H01L29/40 ,  H01L29/423

Abstract: Disclosed are optimized contract structures and fabrication techniques thereof. At least one aspect includes a semiconductor die. The semiconductor die includes a substrate and a contact disposed within the substrate. The contact includes a first portion with a first vertical cross-section having a first cross-sectional area. The first vertical cross-section has a first width and a first height. The contact also includes a second portion with a second vertical cross-section having a second cross-sectional area less than the first cross-sectional area. The second vertical cross-section includes a lower portion having the first width and a second height less than the first height, and an upper portion disposed above the lower portion and having a second width less than the first width and having a third height less than the first height.

公开(公告)号：US20220108983A1

公开(公告)日：2022-04-07

申请号：US17061941

申请日：2020-10-02

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  Ye LU ,  Chenjie TANG ,  Peijie FENG

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/78

Abstract: Certain aspects of the present disclosure relate to a semiconductor device (e.g., a gate-all-around (GAA) semiconductor device) comprising at least one superlattice fin. One example superlattice fin includes a first plurality of nanosheets composed of a first semiconductor material and a second plurality of nanosheets composed of a second semiconductor material, the second semiconductor material being different from the first semiconductor material, wherein a width of a first nanosheet in the first plurality of nanosheets differs from a width of a second nanosheet in the second plurality of nanosheets, the second nanosheet being adjacent to the first nanosheet.

公开(公告)号：US20220068703A1

公开(公告)日：2022-03-03

申请号：US17002127

申请日：2020-08-25

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  John Jianhong ZHU ,  Periannan CHIDAMBARAM

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Disclosed are examples of interconnect structures, e.g., in semiconductor packages. The interconnect structures may include metal lines with graphene. Graphene aids in reducing resistivity of metals used in interconnects. Graphene also serves as diffusion barriers. These properties are advantages when critical dimensions of conductive structures are reduced.

公开(公告)号：US20210143056A1

公开(公告)日：2021-05-13

申请号：US16676715

申请日：2019-11-07

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong ZHU ,  Junjing BAO ,  Giridhar NALLAPATI

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528

Abstract: Certain aspects of the present disclosure generally relate to methods of fabricating integrated circuits. An example method generally includes forming a first cavity in a first layer disposed above a second layer and filling at least a portion of the first cavity with a dielectric material disposed above the second layer. The method further includes forming a second cavity in the dielectric material such that the dielectric material remaining in the first cavity is disposed on (e.g., conforms to) lateral surfaces of the first layer in the first cavity and forming a dielectric spacer comprising a segment of the remaining dielectric material in the first cavity. The method also includes forming a first conductor, in the first layer or the second layer, that is laterally spaced from a second conductor based at least in part on a width of the dielectric spacer.