公开(公告)号：US20160240437A1

公开(公告)日：2016-08-18

申请号：US15141198

申请日：2016-04-28

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Choh Fei YEAP ,  Zhongze WANG ,  Niladri MOJUMDER ,  Mustafa BADAROGLU

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76879 ,  H01L21/02167 ,  H01L21/76829 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76883 ,  H01L21/76895 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53257 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Systems and methods are directed to an integrated circuit comprising a reduced height M1 metal line formed of an exemplary material with lower mean free path than Copper, for local routing of on-chip circuit elements of the integrated circuit, wherein the height of the reduced height M1 metal line is lower than a minimum allowed or allowable height of a conventional M1 metal line formed of Copper. The exemplary materials for forming the reduced height M1 metal line include Tungsten (W), Molybdenum (Mo), and Ruthenium (Ru), wherein these exemplary materials also exhibit lower capacitance and lower RC delays than Copper, while providing high electromigration reliability.

公开(公告)号：US20160093364A1

公开(公告)日：2016-03-31

申请号：US14499147

申请日：2014-09-27

Applicant: QUALCOMM Incorporated

Inventor： Seong-Ook JUNG ,  Younghwi YANG ,  Stanley Seungchul SONG ,  Zhongze WANG ,  Choh Fei YEAP

IPC: G11C11/419

CPC classification number: G11C11/419

Abstract: Systems and methods include a static random-access memory (SRAM) bit cell circuit having an access transistor configured to pass a read current to a storage node, the access transistor including an access transistor back gate. The access transistor back gate is biased to enable selective current boosting of the read current during a read operation.

Abstract translation: 系统和方法包括具有存取晶体管的静态随机存取存储器（SRAM）位单元电路，存取晶体管被配置为将读取电流传递到存储节点，存取晶体管包括存取晶体管背栅极。 存取晶体管背栅极被偏置以使得在读取操作期间读取电流的选择性电流升高。

公开(公告)号：US20150325514A1

公开(公告)日：2015-11-12

申请号：US14274378

申请日：2014-05-09

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan MOJUMDER ,  Zhongze WANG ,  Stanley Seungchul SONG ,  Choh Fei YEAP

IPC: H01L23/522 ,  H01L21/768 ,  H01L27/11

CPC classification number: H01L27/1104 ,  H01L27/0207

Abstract: A static random access memory (SRAM) cell includes a first conductive layer including a wordline landing pad extending into a neighboring memory cell in an adjacent row of a memory array. The wordline landing pad in the first conductive layer is electrically isolated from all gate contacts of the neighboring memory cell. The SRAM cell also includes a second conductive layer including a wordline coupled to the wordline landing pad in the first conductive layer. The SRAM cell further includes a first via coupling a gate contact of a pass transistor gate in the SRAM cell to the wordline landing pad in the first conductive layer. The SRAM cell also includes a second via coupling the wordline landing pad and the wordline of the second conductive layer.

Abstract translation: 静态随机存取存储器（SRAM）单元包括第一导电层，其包括延伸到存储器阵列的相邻行中的相邻存储器单元的字线着陆焊盘。 第一导电层中的字线着陆焊盘与相邻存储器单元的所有栅极触点电隔离。 SRAM单元还包括第二导电层，其包括耦合到第一导电层中的字线着陆焊盘的字线。 SRAM单元进一步包括将SRAM单元中的通过晶体管栅极的栅极接触耦合到第一导电层中的字线着陆焊盘的第一通孔。 SRAM单元还包括耦合字线着陆焊盘和第二导电层的字线的第二通孔。

公开(公告)号：US20150317426A1

公开(公告)日：2015-11-05

申请号：US14498939

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Niladri Narayan MOJUMDER ,  Zhongze WANG ,  Choh Fei YEAP

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/505 ,  G06F2217/78 ,  G06F2217/84

Abstract: Integrated circuit (IC) technology design may include binning data paths of an IC device of a current technology node to bins based on a performance of each of the data paths. Each of the plurality of bins is mapped to a representative circuit unit data path configured according to a predetermined set of electrical and/or physical parameters. The representative circuit unit data paths are calibrated according to updated electrical and/or physical parameters to increase the performance of the representative circuit unit data paths to improve the performance of the IC device in an advanced technology node.

Abstract translation: 集成电路（IC）技术设计可以包括基于每个数据路径的性能来对当前技术节点的IC设备的分组数据路径进行分组。 多个箱中的每一个被映射到根据预定的一组电和/或物理参数配置的代表性电路单元数据路径。 代表性的电路单元数据路径根据更新的电和/或物理参数进行校准，以增加代表性电路单元数据路径的性能，以提高先进技术节点中的IC器件的性能。

公开(公告)号：US20150194339A1

公开(公告)日：2015-07-09

申请号：US14283162

申请日：2014-05-20

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Kern RIM ,  Zhongze WANG ,  Jeffrey Junhao XU ,  Xiangdong CHEN ,  Choh Fei YEAP

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76802 ,  H01L21/76814 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/48 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of fabricating middle of line (MOL) layers and devices including MOL layers. A method in accordance with an aspect of the present disclosure includes depositing a hard mask across active contacts to terminals of semiconductor devices of a semiconductor substrate. Such a method also includes patterning the hard mask to selectively expose some of the active contacts and selectively insulate some of the active contacts. The method also includes depositing a conductive material on the patterned hard mask and the exposed active contacts to couple the exposed active contacts to each other over an active area of the semiconductor devices.

Abstract translation: 制造中间线（MOL）层和包括MOL层的器件的方法。 根据本公开的一个方面的方法包括将半导体衬底的半导体器件的端子上的活性触点沉积硬掩模。 这种方法还包括图案化硬掩模以选择性地暴露一些有源触点并选择性地绝缘一些有源触点。 该方法还包括在图案化的硬掩模和暴露的有源触点上沉积导电材料，以将暴露的有源触点彼此连接在半导体器件的有效区域上。