公开(公告)号：US07200032B2

公开(公告)日：2007-04-03

申请号：US10923651

申请日：2004-08-20

Applicant: Daniel Braun ,  Richard Ferrant

Inventor： Daniel Braun ,  Richard Ferrant

IPC: G11C11/00

CPC classification number: H01L27/224 ,  B82Y10/00 ,  G11C11/15 ,  G11C11/1655 ,  G11C11/1659 ,  H01L27/228

Abstract: A magnetic memory element comprising a magnetic storage element having at least one magnetic layer made of a magnetic material and being vertically oriented relative to a wafer surface on which the magnetic memory element is formed, the magnetic layer having a magnetic anisotropy with its magnetization vector being magnetically coupled to at least one current line, and a magnetic sensor element for sensing the magnetization of the at least one magnetic layer of the magnetic storage element comprising at least one magnetic layer having a magnetization vector being magnetically coupled to the magnetization vector of the at least one magnetic layer of the magnetic storage element, the magnetic sensor element being conductively coupled to the at least one current line.

Abstract translation: 一种磁存储元件，包括磁存储元件，所述磁存储元件具有至少一个由磁性材料制成的磁性层，并且相对于其上形成有磁存储元件的晶片表面垂直取向，所述磁性层具有磁各向异性，其磁化矢量为 磁耦合到至少一个电流线，以及磁传感器元件，用于感测磁存储元件的至少一个磁性层的磁化，包括至少一个磁性层，磁化矢量磁耦合到磁场的磁化矢量 所述磁存储元件的至少一个磁性层，所述磁传感器元件导电地耦合到所述至少一个电流线。

公开(公告)号：US07085153B2

公开(公告)日：2006-08-01

申请号：US10829877

申请日：2004-04-22

Applicant: Richard Ferrant ,  Serguei Okhonin ,  Eric Carman ,  Michel Bron

Inventor： Richard Ferrant ,  Serguei Okhonin ,  Eric Carman ,  Michel Bron

IPC: G11C11/24

CPC classification number: G11C16/28 ,  G11C11/404 ,  G11C2211/4013 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/7841

Abstract: There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory cell and technique of reading data from and writing data into that memory cell. In this regard, in one embodiment of this aspect of the invention, the memory cell includes two transistors which store complementary data states. That is, the two-transistor memory cell includes a first transistor that maintains a complementary state relative to the second transistor. As such, when programmed, one of the transistors of the memory cell stores a logic low (a binary “0”) and the other transistor of the memory cell stores a logic high (a binary “1”). The data state of the two-transistor complementary memory cell may be read and/or determined by sampling, sensing measuring and/or detecting the polarity of the logic states stored in each transistor of complementary memory cell. That is, the two-transistor complementary memory cell is read by sampling, sensing measuring and/or detecting the difference in signals (current or voltage) stored in the two transistors.

Abstract translation: 这里描述和说明了许多发明。 在第一方面，本发明涉及从该存储单元读取数据并将数据写入该存储单元的存储单元和技术。 在这方面，在本发明的这个方面的一个实施例中，存储单元包括存储互补数据状态的两个晶体管。 也就是说，双晶体管存储单元包括相对于第二晶体管保持互补状态的第一晶体管。 这样，当被编程时，存储单元的一个晶体管存储逻辑低（二进制“0”），并且存储单元的另一晶体管存储逻辑高（二进制“1”）。 可以通过采样，感测测量和/或检测存储在互补存储器单元的每个晶体管中的逻辑状态的极性来读取和/或确定双晶体管互补存储单元的数据状态。 也就是说，通过采样，感测测量和/或检测存储在两个晶体管中的信号（电流或电压）的差异来读取双晶体管互补存储单元。

公开(公告)号：US07057916B2

公开(公告)日：2006-06-06

申请号：US10717223

申请日：2003-11-19

Applicant: Richard Ferrant

Inventor： Richard Ferrant

IPC: G11C17/00

CPC classification number: G11C7/067 ,  G11C17/123

Abstract: The invention concerns a ROM circuit (40) including columns of storage cells, each column being connected to a bit site (BLi, BLi+1), wherein the columns are arranged in groups of two adjacent columns, each column of a group capable of being selectively activated relative to the other column of the group, thereby enabling the elimination of a connection to the ground of columns and the design of efficient reading amplifiers.

Abstract translation: 本发明涉及包括存储单元列的ROM电路（40），每列连接到位位（BLi，BLi + 1），其中列排列成两列相邻的列，每列能够 相对于该组的另一列被选择性地激活，从而能够消除与列的接地连接以及有效读取放大器的设计。

公开(公告)号：US20060067098A1

公开(公告)日：2006-03-30

申请号：US10955836

申请日：2004-09-30

Applicant: Richard Ferrant

Inventor： Richard Ferrant

IPC: G11C15/00

CPC classification number: G11C13/0004 ,  G11C15/02 ,  G11C15/046

Abstract: A content addressable memory cell is described. In one embodiment, the content addressable memory cell includes first and second resistive memory elements being coupled in a first series connection and being connected between a first potential value and a second potential value being smaller than said first potential value, and means for their switching between states exhibiting different electric resistance values. The memory cell includes a first field effect transistor and a second field effect transistor, said first and second transistors having drain-source-paths and gate electrodes, said drain-source-paths of said first and second transistors being connected in a second series connection and being connected to at least one of first current lines. The first current line is connected to a potential value level detector for sensing a potential difference as to said third potential value.

公开(公告)号：US20060024886A1

公开(公告)日：2006-02-02

申请号：US10903722

申请日：2004-07-30

Applicant: Richard Ferrant ,  Daniel Braun ,  Pascal Louis

Inventor： Richard Ferrant ,  Daniel Braun ,  Pascal Louis

IPC: H01L21/336

CPC classification number: H01L27/224

Abstract: A MRAM storage device comprises a substrate, on/above of which a plurality of word lines, a plurality of bit lines, a plurality of memory cells, and a plurality of isolation diodes are provided. Each memory cell forms a resistive cross point of one word line and one bit line, respectively. Each memory cell is connected to one isolation diode such that a unidirectional conductive path is formed from a word line to a bit line via the corresponding memory cell, respectively. The substrate, at least a part of the word lines or at least a part of the bit lines, and the isolation diodes are realized as one common monocrystal semiconductor block.

Abstract translation: MRAM存储设备包括其上/其上提供有多个字线，多个位线，多个存储器单元和多个隔离二极管的衬底。 每个存储单元分别形成一个字线和一个位线的电阻交叉点。 每个存储单元连接到一个隔离二极管，使得单向导电路径分别通过对应的存储单元从字线形成到位线。 基板，字线的至少一部分或位线的至少一部分以及隔离二极管被实现为一个常见的单晶半导体块。

公开(公告)号：US06801467B2

公开(公告)日：2004-10-05

申请号：US10186289

申请日：2002-06-27

Applicant: Richard Ferrant ,  Florent Vautrin

Inventor： Richard Ferrant ,  Florent Vautrin

IPC: G11C700

CPC classification number: G11C11/406

Abstract: A device and a method for refreshing the voltage of a circuit line that provides the capability of bringing the circuit line to a ground voltage or to a first voltage. The method provides storing the circuit line voltage in a capacitor; and controlling, by means of the stored voltage, a switch connecting the circuit line to a second voltage of absolute value greater than the first voltage, whereby the circuit line is set to the second voltage if, during the step of storing, the circuit line was at the first voltage.

Abstract translation: 一种用于刷新电路线路的电压的装置和方法，其提供使电路线路接地电压或第一电压的能力。 该方法提供将电路线电压存储在电容器中; 以及通过所存储的电压来控制将所述电路线连接到绝对值大于所述第一电压的第二电压的开关，由此在所述电路线路的存储步骤期间将所述电路线设置为所述第二电压 处于第一电压。

公开(公告)号：US06455884B1

公开(公告)日：2002-09-24

申请号：US09634233

申请日：2000-08-08

Applicant: Tsiu Chiu Chan ,  Antonio Imbruglia ,  Richard Ferrant

Inventor： Tsiu Chiu Chan ,  Antonio Imbruglia ,  Richard Ferrant

IPC: H01L27108

CPC classification number: H01L27/10805 ,  H01L21/76224 ,  H01L21/765 ,  H01L27/10808 ,  Y10S257/921

Abstract: A radiation hardened memory device includes active gate isolation structures placed in series with conventional oxide isolation regions between the active regions of a memory cell array. The active gate isolation structure includes a gate oxide and polycrystalline silicon gate layer electrically coupled to a voltage potential resulting in an active gate isolation structure that prevents a conductive channel extending from adjacent active regions from forming. The gate oxide of the active gate isolation structures is relatively thin compared to the conventional oxide isolation regions and thus, will be less susceptible to any adverse influence from trapped charges caused by radiation exposure.

Abstract translation: 辐射硬化的存储器件包括与存储器单元阵列的有源区之间的常规氧化物隔离区域串联布置的有源栅极隔离结构。 有源栅极隔离结构包括电耦合到电压电位的栅极氧化物和多晶硅栅极层，导致有源栅极隔离结构，其防止从相邻有源区域延伸的导电沟道形成。 与常规的氧化物隔离区域相比，有源栅极隔离结构的栅极氧化物相对较薄，因此不太容易受到由辐射暴露引起的俘获电荷的任何不利影响。

公开(公告)号：US06452841B1

公开(公告)日：2002-09-17

申请号：US09721470

申请日：2000-11-22

Applicant: Richard Ferrant

Inventor： Richard Ferrant

IPC: G11C1156

CPC classification number: G11C7/106 ,  G11C7/06 ,  G11C7/103 ,  G11C7/1051 ,  G11C7/1069 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/412 ,  G11C2207/2245

Abstract: A dynamic random access memory device includes a memory plane including at least one first matrix of memory cells, a read/write amplifier connected to the end of each column of the matrix, and at least one pair of input/output lines associated with the matrix. The dynamic random access memory device also includes at least one cache memory stage connected to each amplifier and is disposed in the immediate vicinity of this amplifier. The cache memory stage includes a static random access memory cell connected between the read/write amplifier and the pair of input/output lines.

Abstract translation: 动态随机存取存储器件包括存储器平面，该存储器平面包括至少一个存储单元的第一矩阵，连接到该矩阵的每列的末端的读/写放大器以及与矩阵相关联的至少一对输入/输出线 。 动态随机存取存储器还包括连接到每个放大器的至少一个高速缓存存储器级并且被布置在该放大器的紧邻附近。 高速缓冲存储器级包括连接在读/写放大器和输入/输出对之间的静态随机存取存储单元。

公开(公告)号：US06215706B1

公开(公告)日：2001-04-10

申请号：US09276603

申请日：1999-03-25

Applicant: Michel Harrand ,  Richard Ferrant

Inventor： Michel Harrand ,  Richard Ferrant

IPC: G11C0700

CPC classification number: G11C7/103

Abstract: The present invention relates to a DRAM circuit including a plurality of memory cells organized in an array, including switches for associating with each end of each column of the array at least two latches controlled independently from each other to store data written into or read from the considered column.

Abstract translation: DRAM电路技术领域本发明涉及一种包括以阵列组织的多个存储单元的DRAM电路，包括用于与阵列的每一列的每一端相关联的开关，该至少两个锁存器互相独立地控制，以存储写入或读取数据的数据 考虑列。

公开(公告)号：US6018486A

公开(公告)日：2000-01-25

申请号：US93210

申请日：1998-06-08

Applicant: Richard Ferrant

Inventor： Richard Ferrant

IPC: G11C7/06 ,  G11C11/4091 ,  G11C7/00

CPC classification number: G11C11/4091 ,  G11C7/06

Abstract: A method is for reading a dynamic memory and a memory implementing the method. The memory includes at least one bit line, one word line, one storage cell accessible by the bit line and the word line, and one reference line, the storage cell enabling the storage of an initial potential representing a logic information. The method includes a step for the precharging of the bit line and the reference line, to carry the potential of these lines to the level of a reference potential that is different from the initial potential stored in the storage cell and a step for the selection of the storage cell to produce a modification of the potential of the bit line and thus create an initial difference between the potentials of the bit line and the reference line. It also includes a step for discharging the bit line and the reference line and a step for the production of an output signal whose state represents values of the discharge currents.

Abstract translation: 一种用于读取动态存储器和实现该方法的存储器的方法。 存储器包括至少一个位线，一个字线，由位线和字线可访问的一个存储单元以及一个参考线，该存储单元能够存储表示逻辑信息的初始电位。 该方法包括用于对位线和参考线进行预充电的步骤，以将这些线的电位传送到与存储单元中存储的初始电位不同的参考电位的电平，以及用于选择 该存储单元产生位线的电位的修改，从而产生位线和参考线的电位之间的初始差。 它还包括用于放电位线和参考线的步骤以及用于产生其状态表示放电电流值的输出信号的步骤。