公开(公告)号：US20070187736A1

公开(公告)日：2007-08-16

申请号：US11737693

申请日：2007-04-19

申请人： Satoru AKIYAMA ,  Riichiro Takemura ,  Takayuki Kawahara ,  Tomonori Sekiguchi

发明人： Satoru AKIYAMA ,  Riichiro Takemura ,  Takayuki Kawahara ,  Tomonori Sekiguchi

IPC分类号： H01L29/94

CPC分类号： G11C11/4091 ,  G11C7/065 ,  G11C2207/065 ,  H01L27/10897

摘要： A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pull-down circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation.

摘要翻译： 构造读出放大器以减少存储器读取操作中的故障的发生，并因此由于读出放大器随着进一步的封闭而增加偏移而降低了芯片产量。 读出放大器电路由多个下拉电路和上拉电路构成，并且多个下拉电路之一中的晶体管具有常数，例如通道长度或通道宽度大于 另一个下拉电路中的晶体管。 首先激活具有较大的晶体管常数的下拉电路，然后激活另一个下拉电路和上拉电路以执行读取操作。

公开(公告)号：US06538945B2

公开(公告)日：2003-03-25

申请号：US10050561

申请日：2002-01-18

申请人： Riichiro Takemura ,  Tsugio Takahashi ,  Masayuki Nakamura ,  Ryo Nagai ,  Norikatsu Takaura ,  Tomonori Sekiguchi ,  Shinichiro Kimura

发明人： Riichiro Takemura ,  Tsugio Takahashi ,  Masayuki Nakamura ,  Ryo Nagai ,  Norikatsu Takaura ,  Tomonori Sekiguchi ,  Shinichiro Kimura

IPC分类号： G11C700

CPC分类号： G11C7/065 ,  G11C11/4091 ,  H01L21/823807 ,  H01L27/092 ,  H01L27/10873 ,  H01L27/10897

摘要： Providing a semiconductor device which lessen influence of the transistor threshold voltage deviation that is one of noise elements when the sense amplifiers are amplified, and which are capable of accurately sensing and amplifying micro signals having read from the memory cells in the sense amplifiers. In a DRAM chip, P+-type gate PMOSs of P+-type polysilicon gates each having a low impurity density of channel and N+-type gate NMOSs of N+-type polysilicon gates are used in a sense amplifier cross coupling section to further increase substrate voltages of the PMOSs and to decrease substrate voltages of the NMOS. For this reason, a deviation of threshold voltage caused by channel implantation is reduced, and a small signal generated on a data line at a read operation of a low-potential memory array is accurately sensed and amplified by a sense amplifier. In addition, the threshold voltages are increased by a substrate bias effect, and a leakage current in a sense amplifier data holding state is reduced.

公开(公告)号：US20120249180A1

公开(公告)日：2012-10-04

申请号：US13429056

申请日：2012-03-23

申请人： Takamasa SUZUKI ,  Akira Kotabe ,  Tomonori Sekiguchi ,  Riichiro Takemura

发明人： Takamasa SUZUKI ,  Akira Kotabe ,  Tomonori Sekiguchi ,  Riichiro Takemura

IPC分类号： H03K19/0175

CPC分类号： H03K3/35613

摘要： A device is disclosed herein, which may be used a level-shift circuit. The device includes first, second and third power supply lines supplied respectively with first, second and third power voltages that are different from one another, first and second input terminals and an output terminal, an output circuit coupled to the first power supply line, the first and second input terminals and the output terminal, a first inverter including an input node coupled to the first input terminal and an output node coupled to the second input terminal, a first transistor coupled in series to the first inverter between the second and third power supply lines, the fifth transistor being rendered non-conductive to deactivate the first inverter, and a control circuit configured to prevent the output terminal from being brought into an electrical floating state during deactivation of the first inverter.

摘要翻译： 本文公开了一种可用于电平移位电路的装置。 该装置包括分别提供彼此不同的第一，第二和第三电源电压的第一，第二和第三电源线，第一和第二输入端子和输出端子，耦合到第一电源线的输出电路， 第一和第二输入端子和输出端子，第一反相器，包括耦合到第一输入端子的输入节点和耦合到第二输入端子的输出节点，在第二和第三功率之间串联耦合到第一反相器的第一晶体管 电源线，使第五晶体管不导通以使第一反相器停用;以及控制电路，被配置为在第一反相器停用期间防止输出端子进入电浮动状态。

公开(公告)号：US20110176379A1

公开(公告)日：2011-07-21

申请号：US13008408

申请日：2011-01-18

申请人： Shinichi TAKAYAMA ,  Akira Kotabe ,  Kazuo Ono ,  Tomonori Sekiguchi ,  Yoshimitsu Yanagawa ,  Riichiro Takemura

发明人： Shinichi TAKAYAMA ,  Akira Kotabe ,  Kazuo Ono ,  Tomonori Sekiguchi ,  Yoshimitsu Yanagawa ,  Riichiro Takemura

IPC分类号： G11C7/06

CPC分类号： G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/002

摘要： A semiconductor memory device includes: first and second bit lines of an open bit-line system; a sense amplifier that amplifies a potential difference between the first and second bit lines; a pair of first and second local data lines corresponding to the first and second bit lines, respectively; and a write amplifier circuit. The write amplifier circuit changes a potential of the second local data line without changing a potential of the first local data line at a time of writing data for the first bit line, and changes a potential of the first local data line without changing a potential of the second local data line at a time of writing data for the second bit line.

摘要翻译： 半导体存储器件包括：开放位线系统的第一和第二位线; 读出放大器，放大第一和第二位线之间的电位差; 对应于第一和第二位线的一对第一和第二本地数据线; 和写放大器电路。 写入放大器电路在写入第一位线的数据时改变第二本地数据线的电位而不改变第一本地数据线的电位，并且在不改变第一本地数据线的电位的情况下改变第一本地数据线的电位 在第二位线的数据写入时的第二本地数据线。

公开(公告)号：US20090086551A1

公开(公告)日：2009-04-02

申请号：US12285204

申请日：2008-09-30

申请人： Akira Ide ,  Yasuhiro Takai ,  Riichiro Takemura ,  Tomonori Sekiguchi

发明人： Akira Ide ,  Yasuhiro Takai ,  Riichiro Takemura ,  Tomonori Sekiguchi

IPC分类号： G11C7/00 ,  G06F11/00 ,  G06F11/10 ,  G11C8/00

CPC分类号： G11C11/4093 ,  G06F11/1004 ,  G11C7/1006 ,  G11C7/1012 ,  G11C8/12

摘要： Disclosed is a semiconductor device in which In case a data group output from a first output pin in a first word configuration is output from the first output pin and a second output pin in a second word configuration, and a data group output from a third output pin in a first word configuration is output from the third output pin and a fourth output pin in a second word configuration, the second output pin is arranged adjacent to the first output pin, and the fourth output pin is arranged adjacent to the third output pin.

摘要翻译： 公开了一种半导体器件，其中如果以第一字配置从第一输出引脚输出的数据组以第二字配置从第一输出引脚和第二输出引脚输出，并且从第三输出输出数据组 第一字配置中的引脚以第二字配置从第三输出引脚和第四输出引脚输出，第二输出引脚被布置为与第一输出引脚相邻，并且第四输出引脚被布置为与第三输出引脚 。

公开(公告)号：US20070153617A1

公开(公告)日：2007-07-05

申请号：US11652012

申请日：2007-01-11

申请人： Tomonori Sekiguchi ,  Riichiro Takemura ,  Takeshi Sakata ,  Kazushige Ayukawa ,  Takayuki Kawahara

发明人： Tomonori Sekiguchi ,  Riichiro Takemura ,  Takeshi Sakata ,  Kazushige Ayukawa ,  Takayuki Kawahara

IPC分类号： G11C7/02

CPC分类号： G11C7/1051 ,  G11C5/025 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C11/405 ,  G11C11/4096 ,  G11C2207/107

摘要： A DRAM adopting a single-intersection memory cell array having randomly accessible data registers accessed whenever the chip is accessed externally. When data items recorded in the data registers are simultaneously written in the memory cell array, the data items are encoded. When data items are read from the memory cell array into the data registers, the data items are decoded. The margin is enhanced because array noise derived from reading is reduced. In addition, the access time of the DRAM is also reduced.

摘要翻译： 采用具有随机访问的数据寄存器的单交叉存储单元阵列的DRAM，只要芯片被外部访问即可。 当记录在数据寄存器中的数据项被同时写入存储单元阵列时，对数据项进行编码。 当将数据项从存储单元阵列读入数据寄存器时，数据项被解码。 由于从读数导出的阵列噪声减小，因此边缘被增强。 另外，DRAM的存取时间也减少了。

公开(公告)号：US06917552B2

公开(公告)日：2005-07-12

申请号：US10671464

申请日：2003-09-29

申请人： Riichiro Takemura ,  Tomonori Sekiguchi ,  Takeshi Sakata

发明人： Riichiro Takemura ,  Tomonori Sekiguchi ,  Takeshi Sakata

IPC分类号： G11C7/00 ,  G11C7/06 ,  G11C11/4091 ,  G11C11/4097

CPC分类号： G11C7/062 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/4097

摘要： Disclosed is a sense amplifier arrangement that achieves high-speed access and shorter cycle time when array voltage is lowered in a DRAM. In a TG clocking sense system to separate data lines between the array side and the sense amplifier side in an early stage of a sensing period, a restore amplifier RAP is added, which amplifies data lines on the array side by referring to the data in the sense amplifier, and the restore amplifier is driven by a voltage VDH higher than the array voltage VDL. As a result, high-speed sense operation of the TG clocking system is made compatible with high-speed restore operation of overdrive system, and it is possible to achieve high-speed access operation and shorter cycle time.

公开(公告)号：US20050146960A1

公开(公告)日：2005-07-07

申请号：US11048915

申请日：2005-02-03

申请人： Tomonori Sekiguchi ,  Riichiro Takemura ,  Takeshi Sakata ,  Kazushige Ayukawa ,  Takayuki Kawahara

发明人： Tomonori Sekiguchi ,  Riichiro Takemura ,  Takeshi Sakata ,  Kazushige Ayukawa ,  Takayuki Kawahara

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C11/401 ,  G11C11/404 ,  G11C11/409 ,  G11C11/4096 ,  G11C15/00

CPC分类号： G11C7/1051 ,  G11C5/025 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C11/405 ,  G11C11/4096 ,  G11C2207/107

摘要： A DRAM adopting a single-intersection memory cell array having randomly accessible data registers accessed whenever the chip is accessed externally. When data items recorded in the data registers are simultaneously written in the memory cell array, the data items are encoded. When data items are read from the memory cell array into the data registers, the data items are decoded. The margin is enhanced because array noise derived from reading is reduced. In addition, the access time of the DRAM is also reduced.

摘要翻译： 采用具有随机访问的数据寄存器的单交叉存储单元阵列的DRAM，只要芯片被外部访问即可。 当记录在数据寄存器中的数据项被同时写入存储单元阵列时，对数据项进行编码。 当将数据项从存储单元阵列读入数据寄存器时，数据项被解码。 由于从读数导出的阵列噪声减小，因此边缘被增强。 另外，DRAM的存取时间也减少了。

公开(公告)号：US20050056876A1

公开(公告)日：2005-03-17

申请号：US10975494

申请日：2004-10-29

申请人： Shinichi Miyatake ,  Kazuhiko Kajigaya ,  Kazuyuki Miyazawa ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Takeshi Sakata

发明人： Shinichi Miyatake ,  Kazuhiko Kajigaya ,  Kazuyuki Miyazawa ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Takeshi Sakata

IPC分类号： G11C11/401 ,  G11C7/18 ,  G11C11/403 ,  G11C11/405 ,  G11C11/406 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/0328 ,  H01L31/119

CPC分类号： H01L27/108 ,  G11C7/18 ,  G11C11/403 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4097 ,  G11C2211/4013 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10897 ,  Y10S257/905 ,  Y10S257/906

摘要： A semiconductor memory device is provided which can achieve the high integration, ultra-high speed operation, and significant reduction of power consumption during the information holding time, by reducing the increase in the area of a memory cell and obtaining a period of the ultra-high speed readout time and ensuring a long refresh period at the time of the self refresh. A DRAM employing a one-intersection cell·two cells/bit method has a twin cell structure employing a one-intersection 6 F2 cell, the structure in which: memory cells are arranged at positions corresponding to all of the intersections between a bit-line pair and a word line; and when a half pitch of the word line is defined as F, a pitch of each bit line of the bit-line pair is larger than 2 F and smaller than 4 F. Further, an active region in the silicon substrate, on which a source, channel and drain of the transistor of each memory cell are formed, is obliquely formed relative to the direction of the bit-line pair.

摘要翻译： 提供一种半导体存储器件，其可以通过减少存储器单元的面积的增加并获得超宽带的周期，实现信息保持时间期间的高集成度，超高速度运行和功耗的显着降低， 高速读出时间，确保自刷新时间长的刷新周期。 采用单交点单元两个单元/位方法的DRAM具有采用单交叉6 F 2单元的双单元结构，其结构是：存储单元布置在对应于a 位线对和字线; 并且当字线的半间距被定义为F时，位线对的每个位线的间距大于2F且小于4F。另外，硅衬底中的有源区域 形成每个存储单元的晶体管的源极，沟道和漏极，相对于位线对的方向倾斜地形成。

公开(公告)号：US06538912B2

公开(公告)日：2003-03-25

申请号：US10139330

申请日：2002-05-07

申请人： Riichiro Takemura ,  Tomonori Sekiguchi ,  Katsutaka Kimura ,  Kazuhiko Kajigaya ,  Tsugio Takahashi

发明人： Riichiro Takemura ,  Tomonori Sekiguchi ,  Katsutaka Kimura ,  Kazuhiko Kajigaya ,  Tsugio Takahashi

IPC分类号： G11C1100

CPC分类号： H01L27/10894 ,  G11C11/4097 ,  H01L27/10897

摘要： When a phase shift method is used as lithography where sense amplifiers are alternately placed in a one intersecting-point memory capable of implementing a reduction in the area of a DRAM, it was difficult to layout data lines in a boundary region between sense amplifiers and each memory array. Therefore, there is provided a semiconductor device according to the present invention. In the semiconductor device, two data lines continuous within the sub memory arrays or interposed therebetween are connected to the adjacent sense amplifiers as a system for drawing data lines from sub memory arrays (SMA) to sense amplifiers (SA) when the sense amplifiers are alternately placed. Namely, the number of data lines interposed between data lines respectively connected to two adjacent sense amplifiers is set to even numbers (0, 2, 4, . . . ). Owing to the above configuration, a break and a short circuit in a portion where a sense amplifier block and a sub memory array are connected, can be avoided, and a connection layout is facilitated.