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    Semiconductor memory device
    2.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US06992343B2

    公开(公告)日：2006-01-31

    申请号：US10975494

    申请日：2004-10-29

    申请人： Shinichi Miyatake ,  Kazuhiko Kajigaya ,  Kazuyuki Miyazawa ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Takeshi Sakata

    发明人： Shinichi Miyatake ,  Kazuhiko Kajigaya ,  Kazuyuki Miyazawa ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Takeshi Sakata

    IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC分类号： H01L27/108 ,  G11C7/18 ,  G11C11/403 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4097 ,  G11C2211/4013 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10897 ,  Y10S257/905 ,  Y10S257/906

    摘要： A semiconductor memory device is provided which can achieve the high integration, ultra-high speed operation, and significant reduction of power consumption during the information holding time, by reducing the increase in the area of a memory cell and obtaining a period of the ultra-high speed readout time and ensuring a long refresh period at the time of the self refresh. A DRAM employing a one-intersection cell·two cells/bit method has a twin cell structure employing a one-intersection 6F2 cell, the structure in which: memory cells are arranged at positions corresponding to all of the intersections between a bit-line pair and a word line; and when a half pitch of the word line is defined as F, a pitch of each bit line of the bit-line pair is larger than 2F and smaller than 4F. Further, an active region in the silicon substrate, on which a source, channel and drain of the transistor of each memory cell are formed, is obliquely formed relative to the direction of the bit-line pair.

    摘要翻译： 提供一种半导体存储器件，其可以通过减少存储器单元的面积的增加并获得超宽带的周期来实现信息保持时间期间的高集成度，超高速度运行和功耗的显着降低， 高速读出时间，确保自刷新时间长的刷新周期。 采用单交点单元两个单元/比特方法的DRAM具有采用单交叉6F 单元的双单元结构，其结构是：将存储单元布置在与 位线对和字线之间的交点; 并且当字线的半间距被定义为F时，位线对的每个位线的间距大于2F且小于4F。 此外，在硅衬底中形成每个存储单元的晶体管的源极，沟道和漏极的有源区相对于位线对的方向倾斜地形成。

    Semiconductor memory device
    3.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US06828612B2

    公开(公告)日：2004-12-07

    申请号：US10388639

    申请日：2003-03-17

    申请人： Shinichi Miyatake ,  Kazuhiko Kajigaya ,  Kazuyuki Miyazawa ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Takeshi Sakata

    发明人： Shinichi Miyatake ,  Kazuhiko Kajigaya ,  Kazuyuki Miyazawa ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Takeshi Sakata

    IPC分类号： H01L27108

    CPC分类号： H01L27/108 ,  G11C7/18 ,  G11C11/403 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4097 ,  G11C2211/4013 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10897 ,  Y10S257/905 ,  Y10S257/906

    摘要： A semiconductor memory device is provided which can achieve the high integration, ultra-high speed operation, and significant reduction of power consumption during the information holding time, by reducing the increase in the area of a memory cell and obtaining a period of the ultra-high speed readout time and ensuring a long refresh period at the time of the self refresh. A DRAM employing a one-intersection cell·two cells/bit method has a twin cell structure employing a one-intersection 6F2 cell, the structure in which: memory cells are arranged at positions corresponding to all of the intersections between a bit-line pair and a word line; and when a half pitch of the word line is defined as F, a pitch of each bit line of the bit-line pair is larger than 2F and smaller than 4F. Further, an active region in the silicon substrate, on which a source, channel and drain of the transistor of each memory cell are formed, is obliquely formed relative to the direction of the bit-line pair.

    摘要翻译： 提供一种半导体存储器件，其可以通过减少存储器单元的面积的增加并获得超宽带的周期来实现信息保持时间期间的高集成度，超高速度运行和功耗的显着降低， 高速读出时间，确保自刷新时间长的刷新周期。 采用单交点单元两个单元/位方法的DRAM具有采用单交叉6F 2单元的双单元结构，其结构是：存储器单元被布置在对应于位之间的所有交点的位置 线对和字线; 并且当字线的半间距被定义为F时，位线对的每个位线的间距大于2F且小于4F。 此外，在硅衬底中形成每个存储单元的晶体管的源极，沟道和漏极的有源区相对于位线对的方向倾斜地形成。

    Semiconductor memory device
    4.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US06882557B2

    公开(公告)日：2005-04-19

    申请号：US10656351

    申请日：2003-09-05

    申请人： Kazuhiko Kajigaya ,  Hiromasa Noda ,  Shinichi Miyatake ,  Riichiro Takemura ,  Tomonori Sekiguchi ,  Takeshi Sakata

    发明人： Kazuhiko Kajigaya ,  Hiromasa Noda ,  Shinichi Miyatake ,  Riichiro Takemura ,  Tomonori Sekiguchi ,  Takeshi Sakata

    IPC分类号： H01L21/8242 ,  G11C5/06 ,  G11C7/18 ,  G11C11/22 ,  G11C11/401 ,  G11C11/4097 ,  G11C29/50 ,  H01L27/02 ,  H01L27/108

    CPC分类号： G11C29/50 ,  G11C7/18 ,  G11C11/4097 ,  G11C2207/005 ,  G11C2211/4013 ,  H01L27/0207 ,  H01L27/10882 ,  H01L27/10897

    摘要： The contact resistance of each switch is reduced, and the on-resistances of all of the switches are set to be uniform, while the area required for arrangement of bit line selection switches is not increased.The switches are connected to one-side ends of the bit lines provided at the odd-numbered positions, and are connected to the other-side ends of the bit lines provided at the even-numbered positions. A pair of odd-numbered or even-numbered bit lines are connected to the terminals of each sense amplifier, respectively. The memory cells are arranged at predetermined intersection points of the word lies and the bit lines, the number of the predetermined intersection points being equal to half of all the intersection points thereof, in such a manner that when one word line is selected, the memory cells connected to the selected word-line can be electrically connected in such a manner that one memory cell is electrically connected to each terminal of the unit circuits.

    摘要翻译： 每个开关的接触电阻减小，并且所有开关的导通电阻被设置为均匀，而位线选择开关的布置所需的面积不增加。 开关连接到设置在奇数位置的位线的一侧端子，并连接到设置在偶数位置的位线的另一端。 一对奇数或偶数位线分别连接到每个读出放大器的端子。 存储单元被布置在字位置和位线的预定交点处，预定交点的数量等于其所有交点的一半，使得当选择一个字线时，存储器 连接到所选字线的单元可以以一个存储单元电连接到单元电路的每个端子的方式电连接。

    Sense amplifier for semiconductor memory device
    5.
    发明申请
    Sense amplifier for semiconductor memory device 有权
    用于半导体存储器件的检测放大器

    公开(公告)号：US20070147152A1

    公开(公告)日：2007-06-28

    申请号：US11706409

    申请日：2007-02-15

    申请人： Tomonori Sekiguchi ,  Shinichi Miyatake ,  Takeshi Sakata ,  Riichiro Takemura ,  Hiromasa Noda ,  Kazuhiko Kajigaya

    发明人： Tomonori Sekiguchi ,  Shinichi Miyatake ,  Takeshi Sakata ,  Riichiro Takemura ,  Hiromasa Noda ,  Kazuhiko Kajigaya

    IPC分类号： G11C7/02

    CPC分类号： G11C7/062 ,  G11C5/063 ,  G11C7/065 ,  G11C7/08 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/12 ,  G11C7/18 ,  G11C8/08 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4097 ,  G11C29/1201 ,  G11C2207/002 ,  G11C2207/005 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10882 ,  H01L27/10897

    摘要： A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line direction, and further connects a source of the MOS transistor serving as the differential pair to a common source line wired in the word-line direction. Since the direct sense amplifier only in a select map is activated by the column select line and the common source line during an read operation, power consumption is significantly reduced during the read operation. Also, since a parasitic capacitance of the MOS transistor serving as the differential pair is separated from the local IO line, a load capacity of the local IO line is reduced and the read operation is speeded up. In addition, during the read operation, a data pattern dependency of the load capacity of the local IO line is reduced and a post-manufacture test is easily made.

    摘要翻译： 本发明的直接感测放大器结合并隔离：用作差分对并具有连接到位线的栅极的MOS晶体管; 以及通过在位线方向上的RLIO线之间布线的列选择线控制的MOS晶体管，并且还将用作差分对的MOS晶体管的源极连接到在字线方向上布线的公共源极线。 由于在读取操作期间，仅在选择映射中的直接读出放大器被列选择线和公共源极线激活，所以在读取操作期间功耗显着降低。 此外，由于用作差分对的MOS晶体管的寄生电容与本地IO线分离，所以本地IO线的负载容量减小，读取操作加快。 此外，在读取操作期间，本地IO线的负载能力的数据模式相关性降低，并且容易进行后期制造测试。

    Sense amplifier for semiconductor memory device
    7.
    发明申请
    Sense amplifier for semiconductor memory device 有权
    用于半导体存储器件的检测放大器

    公开(公告)号：US20090059702A1

    公开(公告)日：2009-03-05

    申请号：US12285527

    申请日：2008-10-08

    申请人： Tomonori Sekiguchi ,  Shinichi Miyatake ,  Takeshi Sakata ,  Riichiro Takemura ,  Hiromasa Noda ,  Kazuhiko Kajigaya

    发明人： Tomonori Sekiguchi ,  Shinichi Miyatake ,  Takeshi Sakata ,  Riichiro Takemura ,  Hiromasa Noda ,  Kazuhiko Kajigaya

    IPC分类号： G11C7/06

    CPC分类号： G11C7/062 ,  G11C5/063 ,  G11C7/065 ,  G11C7/08 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/12 ,  G11C7/18 ,  G11C8/08 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4097 ,  G11C29/1201 ,  G11C2207/002 ,  G11C2207/005 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10882 ,  H01L27/10897

    摘要： A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line direction, and further connects a source of the MOS transistor serving as the differential pair to a common source line wired in the word-line direction. Since the direct sense amplifier only in a select map is activated by the column select line and the common source line during an read operation, power consumption is significantly reduced during the read operation. Also, since a parasitic capacitance of the MOS transistor serving as the differential pair is separated from the local IO line, a load capacity of the local IO line is reduced and the read operation is speeded up. In addition, during the read operation, a data pattern dependency of the load capacity of the local IO line is reduced and a post-manufacture test is easily made.

    摘要翻译： 本发明的直接感测放大器结合并隔离：用作差分对并具有连接到位线的栅极的MOS晶体管; 以及通过在位线方向上的RLIO线之间布线的列选择线控制的MOS晶体管，并且还将用作差分对的MOS晶体管的源极连接到在字线方向上布线的公共源极线。 由于在读取操作期间，仅在选择映射中的直接读出放大器被列选择线和公共源极线激活，所以在读取操作期间功耗显着降低。 此外，由于用作差分对的MOS晶体管的寄生电容与本地IO线分离，所以本地IO线的负载容量减小，读取操作加快。 此外，在读取操作期间，本地IO线的负载能力的数据模式相关性降低，并且容易进行后期制造测试。

    Sense amplifier for semiconductor memory device
    8.
    发明授权
    Sense amplifier for semiconductor memory device 有权
    用于半导体存储器件的检测放大器

    公开(公告)号：US07447091B2

    公开(公告)日：2008-11-04

    申请号：US11706409

    申请日：2007-02-15

    申请人： Tomonori Sekiguchi ,  Shinichi Miyatake ,  Takeshi Sakata ,  Riichiro Takemura ,  Hiromasa Noda ,  Kazuhiko Kajigaya

    发明人： Tomonori Sekiguchi ,  Shinichi Miyatake ,  Takeshi Sakata ,  Riichiro Takemura ,  Hiromasa Noda ,  Kazuhiko Kajigaya

    IPC分类号： G11C7/02

    CPC分类号： G11C7/062 ,  G11C5/063 ,  G11C7/065 ,  G11C7/08 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/12 ,  G11C7/18 ,  G11C8/08 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4097 ,  G11C29/1201 ,  G11C2207/002 ,  G11C2207/005 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10882 ,  H01L27/10897

    摘要： A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line direction, and further connects a source of the MOS transistor serving as the differential pair to a common source line wired in the word-line direction. Since the direct sense amplifier only in a select map is activated by the column select line and the common source line during an read operation, power consumption is significantly reduced during the read operation. Also, since a parasitic capacitance of the MOS transistor serving as the differential pair is separated from the local IO line, a load capacity of the local IO line is reduced and the read operation is speeded up. In addition, during the read operation, a data pattern dependency of the load capacity of the local IO line is reduced and a post-manufacture test is easily made.

    摘要翻译： 本发明的直接感测放大器结合并隔离：用作差分对并具有连接到位线的栅极的MOS晶体管; 以及通过在位线方向上的RLIO线之间布线的列选择线控制的MOS晶体管，并且还将用作差分对的MOS晶体管的源极连接到在字线方向上布线的公共源极线。 由于在读取操作期间，仅在选择映射中的直接读出放大器被列选择线和公共源极线激活，所以在读取操作期间功耗显着降低。 此外，由于用作差分对的MOS晶体管的寄生电容与本地IO线分离，所以本地IO线的负载容量减小，读取操作加快。 此外，在读取操作期间，本地IO线的负载能力的数据模式相关性降低，并且容易进行后期制造测试。