-
41.发明授权公开(公告)号：US08377800B2
公开(公告)日：2013-02-19
申请号：US13453848
申请日：2012-04-23
IPC分类号： H01L21/00
CPC分类号： H01L23/544 , G03F7/70633 , G03F9/7076 , H01L2223/54453 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： Mark and method for integrated circuit fabrication with polarized light lithography. A preferred embodiment comprises a first plurality of elements comprised of a first component type, wherein the first component type has a first polarization, and a second plurality of elements comprised of a second component type, wherein the second component type has a second polarization, wherein the first polarization and the second polarization are orthogonal, wherein adjacent elements are of different component types. The alignment marks can be used in an intensity based or a diffraction based alignment process.
摘要翻译： 用偏光光刻技术集成电路制造的标记和方法。 优选实施例包括由第一部件类型构成的第一多个元件，其中第一元件类型具有第一偏振，第二元件类型具有第二元件类型，其中第二元件类型具有第二偏振，其中 第一极化和第二极化是正交的，其中相邻元件是不同的组件类型。 对准标记可以用于基于强度或基于衍射的对准过程。
-
42.发明授权公开(公告)号：US08183129B2
公开(公告)日：2012-05-22
申请号：US12694105
申请日：2010-01-26
IPC分类号： H01L21/00
CPC分类号： H01L23/544 , G03F7/70633 , G03F9/7076 , H01L2223/54453 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： Mark and method for integrated circuit fabrication with polarized light lithography. A preferred embodiment comprises a first plurality of elements comprised of a first component type, wherein the first component type has a first polarization, and a second plurality of elements comprised of a second component type, wherein the second component type has a second polarization, wherein the first polarization and the second polarization are orthogonal, wherein adjacent elements are of different component types. The alignment marks can be used in an intensity based or a diffraction based alignment process.
摘要翻译： 用偏光光刻技术集成电路制造的标记和方法。 优选实施例包括由第一部件类型构成的第一多个元件，其中第一元件类型具有第一偏振，第二元件类型具有第二元件类型，其中第二元件类型具有第二偏振，其中 第一极化和第二极化是正交的，其中相邻元件是不同的组件类型。 对准标记可以用于基于强度或基于衍射的对准过程。
-
公开(公告)号：US20100120177A1
公开(公告)日：2010-05-13
申请号：US12691218
申请日：2010-01-21
IPC分类号： H01L21/66 , H01L21/3065 , H01L21/308 , H01L21/306
CPC分类号： H01L21/32137 , H01L22/12
摘要： A method for manufacturing a semiconductor device is disclosed including determining a dimension or other physical characteristic of a pattern in a layer of material that is disposed on a workpiece, and etching the layer of material using information that is related to the dimension. A system is also disclosed for manufacturing a semiconductor device including a first etch system configured to etch a layer to define a pattern in the layer, and a second etch system configured to measure a physical characteristic of the pattern, determine an etch control parameter based on the physical characteristic, and etch the layer in accordance with the etch control parameter.
摘要翻译： 公开了一种用于制造半导体器件的方法，其包括确定设置在工件上的材料层中的图案的尺寸或其他物理特性，以及使用与所述尺寸相关的信息来蚀刻所述材料层。 还公开了一种用于制造半导体器件的系统，该半导体器件包括被配置为蚀刻层以限定该层中的图案的第一蚀刻系统，以及被配置为测量该图案的物理特性的第二蚀刻系统，基于 物理特性，并根据蚀刻控制参数刻蚀该层。
-
公开(公告)号：US20080286698A1
公开(公告)日：2008-11-20
申请号：US11804528
申请日：2007-05-18
申请人： Haoren Zhuang , Chong Kwang Chang , Alois Gutmann , Jingyu Lian , Matthias Lipinski , Len Yuan Tsou , Helen Wang
发明人： Haoren Zhuang , Chong Kwang Chang , Alois Gutmann , Jingyu Lian , Matthias Lipinski , Len Yuan Tsou , Helen Wang
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/84
摘要： Methods for manufacturing semiconductor devices are disclosed. One preferred embodiment is a method of processing a semiconductor device. The method includes providing a workpiece having a material layer to be patterned disposed thereon. A masking material is formed over the material layer of the workpiece. The masking material includes a lower portion and an upper portion disposed over the lower portion. The upper portion of the masking material is patterned with a first pattern. An additional substance is introduced and the lower portion of the masking material is patterned. The masking material and the additional substance are used to pattern the material layer of the workpiece.
摘要翻译： 公开了制造半导体器件的方法。 一个优选实施例是一种处理半导体器件的方法。 该方法包括提供具有设置在其上的待图案化材料层的工件。 在工件的材料层上形成掩模材料。 掩模材料包括下部和设置在下部上的上部。 用第一图案对掩模材料的上部进行图案化。 引入另外的物质，掩模材料的下部被图案化。 掩模材料和附加物质用于对工件的材料层进行图案化。
-
公开(公告)号：US20080119048A1
公开(公告)日：2008-05-22
申请号：US11602886
申请日：2006-11-21
IPC分类号： H01L21/302
CPC分类号： G03F1/50 , G02B5/3083 , Y10T428/24479
摘要： Lithography masks and methods of manufacture thereof are disclosed. A preferred embodiment comprises a method of manufacturing a lithography mask. The method includes providing a substrate, forming a first pattern in a first region of the substrate, and forming a second pattern in a second region of the substrate, the second pattern comprising patterns for features oriented differently than patterns for features of the first pattern. The method includes affecting a polarization rotation of light differently in the first region than in the second region of the substrate.
摘要翻译： 公开了平版印刷掩模及其制造方法。 优选实施例包括制造光刻掩模的方法。 所述方法包括提供衬底，在所述衬底的第一区域中形成第一图案，以及在所述衬底的第二区域中形成第二图案，所述第二图案包括不同于第一图案特征的图案的图案。 该方法包括在第一区域中比在衬底的第二区域中影响光的偏振旋转。
-
公开(公告)号：US20070239305A1
公开(公告)日：2007-10-11
申请号：US11390696
申请日：2006-03-28
IPC分类号： G06F19/00
摘要： Process control systems and methods for semiconductor device manufacturing are disclosed. A plurality of feedback and feed-forward loops are used to accurately control the critical dimension (CD) of features formed on material layers of semiconductor devices. Semiconductor devices with features having substantially the same dimension for each die across the surface of a wafer may be fabricated using the novel process control systems and methods described herein.
摘要翻译： 公开了用于半导体器件制造的工艺控制系统和方法。 使用多个反馈和前馈环来精确地控制在半导体器件的材料层上形成的特征的临界尺寸（CD）。 可以使用本文所述的新颖的工艺控制系统和方法来制造具有对于晶片表面上的每个管芯具有基本相同尺寸的特征的半导体器件。
-
公开(公告)号：US20060170045A1
公开(公告)日：2006-08-03
申请号：US11047928
申请日：2005-02-01
申请人： Jiang Yan , Chun-Yung Sung , Danny Shum , Alois Gutmann
发明人： Jiang Yan , Chun-Yung Sung , Danny Shum , Alois Gutmann
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L21/76232 , H01L21/76283 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1207 , H01L29/045 , H01L29/78687
摘要： A semiconductor device includes a semiconductor body having semiconductor material of a first crystal orientation. A first transistor is formed in the semiconductor material of the first crystal orientation. An insulating layer overlies portions of the semiconductor body and a semiconductor layer overlies the insulating layer. The semiconductor layer has a second crystal orientation. A second transistor is formed in the semiconductor layer having the second crystal orientation. In the preferred embodiment, the semiconductor body is (100) silicon, the first transistor is an NMOS transistor, the semiconductor layer is (110) silicon and the second transistor is a PMOS transistor.
摘要翻译： 半导体器件包括具有第一晶体取向的半导体材料的半导体本体。 在第一晶体取向的半导体材料中形成第一晶体管。 绝缘层覆盖半导体本体的部分，并且半导体层覆盖绝缘层。 半导体层具有第二晶体取向。 在具有第二晶体取向的半导体层中形成第二晶体管。 在优选实施例中，半导体本体是（100）硅，第一晶体管是NMOS晶体管，半导体层是（110）硅，第二晶体管是PMOS晶体管。
-
公开(公告)号：US07030506B2
公开(公告)日：2006-04-18
申请号：US10685004
申请日：2003-10-15
IPC分类号： H01L23/544
CPC分类号： H01L23/544 , G03F7/70633 , G03F9/7076 , H01L2223/54466 , H01L2924/0002 , Y10T428/24802 , H01L2924/00
摘要： A method and mask to improve measurement of alignment marks is disclosed. An exemplary embodiment of the invention includes a resist mask with a patterned alignment mark comprising an assemblage of features whose spacing is smaller than the wavelength of light used to measure the alignment. In a preferred embodiment, an alignment mark patterning process alters the appearance of the alignment mark and renders an enhanced contrast with the substrate background.
摘要翻译： 公开了一种改善对准标记测量的方法和掩模。 本发明的示例性实施例包括具有图案化对准标记的抗蚀剂掩模，该图案对准标记包括其间隔小于用于测量对准的光的波长的特征的组合。 在优选实施例中，对准标记图案化工艺改变对准标记的外观，并提高与衬底背景的对比度。
-
公开(公告)号：US06954002B2
公开(公告)日：2005-10-11
申请号：US10230493
申请日：2002-08-29
申请人： Shoaib H. Zaidi , Gary Williams , Alois Gutmann
发明人： Shoaib H. Zaidi , Gary Williams , Alois Gutmann
IPC分类号： G03F9/00 , H01L23/544 , H01L29/06
CPC分类号： G03F9/7076
摘要： A semiconductor wafer comprises a semiconductor substrate, a surface alignment mark visible on the semiconductor surface and a plurality of nanostructures on the surface of the surface alignment mark having an average pitch adapted to reduce reflectivity of the surface alignment mark in a predetermined light bandwidth.
摘要翻译： 半导体晶片包括半导体衬底，半导体表面上可见的表面对准标记和表面对准标记表面上的多个纳米结构，其具有适于减小预定光带宽中的表面对准标记的反射率的平均间距。
-
公开(公告)号：US06670646B2
公开(公告)日：2003-12-30
申请号：US10074479
申请日：2002-02-11
申请人： Zhijian Lu , Shahid Butt , Alois Gutmann
发明人： Zhijian Lu , Shahid Butt , Alois Gutmann
IPC分类号： H01L3300
CPC分类号： G03F1/30 , G03F1/36 , G03F7/70441
摘要： A mask (118) and method for patterning a semiconductor wafer. The mask (118) includes apertures (122) and assist lines (124) disposed between apertures (122). The assist lines (124) reduce the diffraction effects of the lithographic process, resulting in improved depth of focus and resolution of patterns on a semiconductor wafer.
-
-
-
-
-
-
-
-
-
搜索结果
75 条记录 (耗时 0.034 秒)
