公开(公告)号：US20240395613A1

公开(公告)日：2024-11-28

申请号：US18794736

申请日：2024-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook SHIN ,  Sanghoon AHN ,  Woojin LEE ,  Kyung-Eun BYUN ,  Junghoo SHIN ,  Hyeonjin SHIN ,  Yunseong LEE

IPC: H01L21/768 ,  H01L21/285

Abstract: Provided is a method of forming an interconnect structure. The method includes preparing a substrate including a first metal layer and a first insulating layer, selectively forming a carbon layer having an sp2 bonding structure on the first metal layer, selectively forming a second insulating layer on the first insulating layer, forming a third insulating layer to cover the second insulating layer, and forming a second metal layer electrically connected to the first metal layer.

公开(公告)号：US20240178294A1

公开(公告)日：2024-05-30

申请号：US18347929

申请日：2023-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunkyu LEE ,  Keunwook SHIN ,  Minsu SEOL

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/18 ,  H01L29/417 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/18 ,  H01L29/41733 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device may include a first electrode and a second electrode on a substrate and arranged perpendicular to a surface of the substrate, a plurality of channel layers between the first electrode and the second electrode, and a gate electrode surrounding the plurality of channel layers. The plurality of channel layers may be inclined with respect to a direction from the first electrode to the second electrode. An electronic device may include the semiconductor device.

公开(公告)号：US20230238329A1

公开(公告)日：2023-07-27

申请号：US18158233

申请日：2023-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook SHIN ,  Sangwon KIM ,  Kyung-Eun BYUN ,  Joungeun YOO ,  Eunkyu LEE ,  Changseok LEE ,  Alum JUNG

IPC: H01L23/532 ,  H01L23/528

CPC classification number: H01L23/53276 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53242

Abstract: An interconnect structure may include a dielectric layer including a trench, a conductive wiring including graphene filling an inside of the trench, and a liner layer in contact with at least one surface of the conductive wiring and including a metal.

公开(公告)号：US20230114933A1

公开(公告)日：2023-04-13

申请号：US17958653

申请日：2022-10-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhyun KIM ,  Kyung-Eun BYUN ,  Keunwook SHIN ,  Changseok LEE ,  Baekwon PARK

IPC: H01L21/02 ,  H01L23/532 ,  C23C16/40 ,  C23C16/455 ,  H01L21/768

Abstract: Provided are a graphene interconnect structure, an electronic device including the graphene interconnect structure, and a method of manufacturing the graphene interconnect structure. The graphene interconnect structure may include: a first oxide dielectric material layer; a second oxide dielectric material layer on a surface of the first oxide dielectric material layer and having a dielectric constant greater than that of the first oxide dielectric material layer; and a graphene layer on a surface of the second oxide dielectric material layer opposite to the surface on which the first oxide dielectric material layer is located.

公开(公告)号：US20230070266A1

公开(公告)日：2023-03-09

申请号：US17670949

申请日：2022-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhyun KIM ,  Seunggeol NAM ,  Keunwook SHIN ,  Dohyun LEE

IPC: H01L29/45 ,  H01L29/417 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes a first source/drain structure including a first semiconductor region and a first electrode in electrical contact with the first semiconductor region; a second source/drain structure including a second semiconductor region and a second electrode in electrical contact with the second semiconductor region; a channel between the first semiconductor region and the second semiconductor region; and a gate structure including a gate insulating film covering the channel and a gate electrode covering the gate insulating film. The first source/drain structure further includes a silicide film between the first semiconductor region and the first electrode and a conductive barrier between the silicide film and the first electrode. The conductive barrier includes a conductive two-dimensional material.

公开(公告)号：US20220068704A1

公开(公告)日：2022-03-03

申请号：US17411467

申请日：2021-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook SHIN ,  Sanghoon AHN ,  Woojin LEE ,  Kyung-Eun BYUN ,  Junghoo SHIN ,  Hyeonjin SHIN ,  Yunseong LEE

IPC: H01L21/768

Abstract: Provided is a method of forming an interconnect structure. The method includes preparing a substrate including a first metal layer and a first insulating layer, selectively forming a carbon layer having an sp2 bonding structure on the first metal layer, selectively forming a second insulating layer on the first insulating layer, forming a third insulating layer to cover the second insulating layer, and forming a second metal layer electrically connected to the first metal layer.

公开(公告)号：US20210210346A1

公开(公告)日：2021-07-08

申请号：US16923478

申请日：2020-07-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook SHIN ,  Kyungeun BYUN ,  Hyeonjin SHIN ,  Soyoung LEE ,  Changseok LEE

IPC: H01L21/02 ,  H01L29/16 ,  C23C16/50 ,  C23C16/26

Abstract: A graphene structure and a method of forming the graphene structure are provided. The graphene structure includes directly grown graphene that is directly grown on a surface of a substrate and has controlled surface energy.

公开(公告)号：US20210159183A1

公开(公告)日：2021-05-27

申请号：US17165246

申请日：2021-02-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Eun BYUN ,  Keunwook SHIN ,  Yonghoon KIM ,  Hyeonjin SHIN ,  Hyunjae SONG ,  Changseok LEE ,  Changhyun KIM ,  Yeonchoo CHO

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

Abstract: Provided are an interconnect structure and an electronic device including the interconnect structure. The interconnect structure includes a dielectric layer including at least one trench, a conductive wiring filling an inside of the at least one trench, and a cap layer on at least one surface of the conductive wiring. The cap layer includes nanocrystalline graphene. The nanocrystalline includes nano-sized crystals.

公开(公告)号：US20200035611A1

公开(公告)日：2020-01-30

申请号：US16215899

申请日：2018-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Eun Byun ,  Keunwook SHIN ,  Yonghoon KIM ,  Hyeonjin SHIN ,  Hyunjae SONG ,  Changseok LEE ,  Changhyun KIM ,  Yeonchoo CHO

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768

Abstract: Provided are an interconnect structure and an electronic device including the interconnect structure. The interconnect structure includes a dielectric layer including at least one trench, a conductive wiring filling an inside of the at least one trench, and a cap layer on at least one surface of the conductive wiring. The cap layer includes nanocrystalline graphene. The nanocrystalline includes nano-sized crystals.

公开(公告)号：US20180149966A1

公开(公告)日：2018-05-31

申请号：US15807106

申请日：2017-11-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjin SHIN ,  Hyunjae SONG ,  Seongjun PARK ,  Keunwook SHIN ,  Changseok LEE

IPC: G03F1/64 ,  G03F1/22 ,  G03F7/20

CPC classification number: G03F1/64 ,  G03F1/22 ,  G03F1/62 ,  G03F7/7015 ,  G03F7/70883

Abstract: A pellicle for a photomask, a reticle including the same, and an exposure apparatus for lithography are provided. The pellicle may include a pellicle membrane, and the pellicle membrane may include nanocrystalline graphene. The nanocrystalline graphene may have defects. The nanocrystalline graphene may include a plurality of nanoscale crystal grains, and the nanoscale crystal grains may include a two-dimensional (2D) carbon structure having an aromatic ring structure. The defects of the nanocrystalline graphene may include at least one of an sp3 carbon atom, an oxygen atom, a nitrogen atom, or a carbon vacancy.